Motorola Corporation

David L Stolfa

Kenneth David Cornett

Jay Paul John

Branko L Avanic

James Albert Kirchgessner

John W Steele

Richard W Mauntel

Vida Ilderem Burger

Michael H Kaneshiro

Ik-Sung Lim

Phillip W Dahl

A method of manufacturing a heterojunction BiCMOS IC. ( ) includes forming a gate electrode ( ), forming a protective layer ( ) over the gate electrode, forming a semiconductor layer ( ) over the protective layer, depositing an electrically insulative layer ( ) over the semiconductor layer, using a mask layer ( ) to define a doped region ( ) in the semiconductor layer and to define a hole ( ) in the electrically insulative layer, forming an electrically conductive layer ( ) over the electrically insulative layer, using another mask layer ( ) to define an emitter region ( ) in the electrically conductive layer and to define an intrinsic base region ( ) and a portion of an extrinsic base region ( ) in the electrically conductive layer, and using yet another mask layer ( ) to define another portion of the extrinsic base region in the electrically conductive layer.

Method of manufacturing a heterojunction BiCMOS integrated circuit

A voltage variable capacitor (10) fabricated on a semiconductor substrate (11) includes a gate structure (62) and a well (22) under the gate structure (62). A heavily doped buried layer (15) and a heavily doped contact region (31) in the semiconductor substrate (11) form a low resistance conduction path from the well (22) to a surface (17) of the semiconductor substrate (11). A multi-finger layout is used to construct the voltage variable capacitor (10). In operation, when a voltage applied across the voltage variable capacitor (10) changes, the width of depletion region in the well (22) changes, and the capacitance of the voltage variable capacitor (10) varies accordingly.

Variable capacitor and method for fabricating the same

A high Q integrated inductor-capacitor (L-C) resonator (200) includes a planar inductor (201) having a plurality of turns and a serially connected first and second capacitor (205, 207) that is connected in parallel with the planar inductor (201). The first and second capacitors (205, 207) are positioned within at least one turn of the planar inductor (201) for reducing the parasitic interconnection resistance between the planar inductor (201) and first and second capacitor (205, 207) and also increasing the Q factor of the L-C resonator.

High Q integrated resonator structure

An analog trim circuit enables and disables one or more serially connected passive elements for setting characteristics of the circuit. Each passive element has a transistor across its first and second conduction terminals operating in response to a control signal from a control circuit for enabling and disabling conduction through the associated passive element. The control circuits are responsive to a data signal for providing the control signals that enable and disable the conduction through the passive elements. The data signal allows a preview of the trimming results. The fuse in certain ones of the control circuits are blown to set the control signals to fixed values after removal of the data signal.

Circuit and method of previewing analog trimming

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Phoenix, AZ, United States of America

David L Stolfa