Gigabus, Inc.

Shographics, Inc.

Technology IP Holdings, Inc.

David L Sherman

Samuel Lee

In accordance with an embodiment of the invention, a semiconductor memory includes a number of data ports each having a predetermined number of data bits. The memory further has a number of memory macros each including at least one memory array having rows and columns of memory cells. Each memory macro further includes a plurality of internal data connection points directly connected to external terminals to transfer data to or from the at least one memory array. The internal data connection points correspond in number to the number of the data ports, and the internal data connection points in the memory macros together form the plurality of data ports.

Multi-ported memory

A search system and method is provided that may implemented in a content addressable memory (CAM) using various different memory technologies including SRAMs. DRAMs or Embedded DRAMs. The search system increases the density and efficiency of the CAM by using a search tree to reduce the total number of entries that must be matched against the key.

Memory device search system and method

A low power, high speed communications bus is provided which may interconnect semiconductor dies or computer modules over short distances. The bus may be operated in either a mesosynchronous mode of operation or asynchronous mode of operation so that the bus does not require a phase locked loop (PLL). In addition, the bus does not require termination due to the programmed `series termination` in combination with strict limits on the time of flight on the bus versus the slew rate of the signals. The bus may also permit the port sizes connected to the bus to be reconfigured on the fly to provide 'quality of service support for buses'. The bus may also provide multiple independent data streams that may be controlled by a single address/command bus. The bus may also provide a pair of wires which carry two signals (e.g., a TStrb/Ren signal on one wire and a RStrb/Ten signal on the other wire) between each port to communicate the strobe signals between the ports.

Low power, high speed communications bus

A mathematical computation circuit to interpolate attribute values along a line between two points where the attributes are known and a video circuit using the interpolation circuit. The interpolation circuit includes a circuit to calculate the rate of change of said attribute between said two points on a raster-scanned display on a per scan line basis and a circuit to add the rate of change of said attribute per scan line to the current attribute value for the current scan line as each new scan line occurs. The sum is used as the new current value. A video system uses multiple instances of this interpolation circuit and includes a sorter to sort vertices records from a display list and send the appropriate attribute data to the interpolation circuits. There rates of change are calculated and attribute values developed for each pixel location. A video control circuit then generates color, saturation and intensity data for use in filling a frame buffer in accordance with addresses generated by an address generation circuit. The frame buffer is then read to generate the display.

Video system with parallel attribute interpolations

A bit serial multiplier suitable for pipelined operations. This multiplier uses a conventional bit serial multiplier cell using Booth's algorithm and stored carry architecture, but modified in several respects. First, the partial product and carry storage registers may be put in a hold state so that their contents remain constant over as many clock cycles as a stall signal is asserted so that data may be inserted in the pipeline without destroying pipeline synchronization. Second, there are added two shift registers one of which parallel loads the partial product bits and the other of which loads the carry bits as each set of bits exists after all the multiplier bits have been shifted into the multiplier. After the parallel loading process, the partial product and carry latches in the main cell are cleared thereby allowing another multiplication with different operands to begin. While this second multiplication is being performed, the partial product and carry bits from the first multiplication are being shifted out of the shift registers to an adder which combines these bits to derive the final product bits. Multiple multiplicand storage registers are provided for allowing prefetch and rapid change of operands and multiple multiplier bit stream control circuitry is provied.

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Fremont, CA, United States of America

David L Sherman