International Business Machines Corporation

David L Rude

William Vincent Huott

K Paul Muller

David S Wolpert

Kevin W Kark

John Greg Massey

Ruchir Puri

Christopher J Berry

Haoxing Ren

Joachim Keinert

Jonathan Yang Chen

Jeremy T Hopkins

Christopher Carney

Vern Anthony Victoria

Eddy St Juste

Smita Krishnaswamy

John Mack Isakson

Nilesh A Modi

Nathan A Dotson

A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

Error protection for a data bus

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

Error protection for integrated circuits

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

Placement of storage cells on an integrated circuit

A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.

Shared error protection for register banks

A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.

Logic difference synthesis

A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage.

Method and system for changing circuits in an integrated circuit

In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

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Wendell, NC, United States of America

David L Rude