Advanced Micro Devices Corporation

Nexgen, Inc.

David L Puziol

Korbin S Van Dyke

Larry Widigen

Walstein Bennett Smith, Iii

Len Shar

Elliot A Sowadsky

In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

Configurable branch prediction for a processor performing speculative execution

In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss Information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

The existing execution units of a high-performance processor are augmented by tile addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.

Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit

Configurable branch prediction for a processor performing speculative

The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.

Pipeline throughput via parallel out-of-order execution of adds and

Processor having primary integer execution unit and supplemental integer

A Branch Prediction Cache (BPC) selects from among multiple branch address entries for a single return-type instruction that returns to multiple callers. The BPC has a branch address associative memory, a return address associative memory, and word line logic used to validate and qualify entries. The branch address associative memory monitors program addresses for previously stored branch addresses. The return address stack (RtnStack) stores the return addresses for the most recent call-type instructions. The top of the stack is input to the return address associative memory. When a program address has multiple matches in the branch address associative memory, the return address associative memory enables only the entry that has an associated return address matching the top of the RtnStack. In an alternate embodiment, the return address associative memory is combined with a branch address cache and target address associative memory.

Branch prediction cache with multiple entries for returns having

An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.

Growing community of inventors

Sunnyvale, CA, United States of America

David L Puziol