Environmental Research Institute of Michigan

Pixel Velocity, Inc.

Other

Norfolk Southern Corporation

David L McCubbrey

Robert M Lougheed

William O Dargel

Ralph E Richardson

Stanley R Sternberg

Thomas Wessling

Gregory Lowe

Robert Rendleman

Joseph Samson

Theron Friedman

Paul Kortesoja

John Blanchfield

Lester Witter

Quentin Holmes

According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.

Scalable system for wide area surveillance

A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.

Method of partitioning an algorithm between hardware and software

An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.

Automated system for designing and developing field programmable gate arrays

The stackable motherboardof the first embodiment includes: a circuit boardhaving a first sideand a second sideopposite the first side, a processormounted on the circuit board, a first peripheral interconnect, and a second peripheral interconnect. The stackable motherboardalso preferably includes: a first motherboard interconnectmounted on the first sideof the circuit boardand adapted to communicate data between the processorand a first auxiliary motherboard, and a second motherboard interconnectmounted on the second sideof the circuit boardand adapted to communicate data between the processorand a second auxiliary motherboard.

Stackable motherboard and related sensor systems

An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O. The mapper includes means for evaluating alternative interconnection routes between logic components within the target FPGA, and means for producing an optimized placement and routing of the logic components and interconnections on the target FPGA. The mapper also generates a low level command listing as a source file that serves as an input file for a conventional low-level FPGA programming tool. From that input file, the tool is able to generate a hardware gate-programming bitstream to be directed to the target FPGA, thereby programming the FPGA with the user-defined algorithm.

A method and an apparatus for identifying a feature of a railway and deploying equipment for servicing same by image processing range data pertaining to the railway feature. The method includes identifying a feature of a railway, wherein the identifying involves processing an image corresponding to ranges to the feature. The apparatus includes a vision system for determining a range to a feature of the railway and means for positioning equipment relative to, for servicing, the feature, based on the range.

Range-finding based image processing rail way servicing apparatus and method

A computer system and a method for a mail sorting operation in which the computer system determines the location of the ZIP code within a digital image of an address block from a piece of mail. An interstroke distance is calculated for the image and the strokes of the image are thinned to enhance vertical separation between the lines of the address block. A medial axis for each line is determined and the medial axis is superimposed upon the digital image. A bleeding operation is conducted on the digital image from the medial axis at which data bits that do not connect to the medial axis are notated as punctuation and interlinear connected strokes are then divided between the two lines. The last line which is determined to be large enough to contain a ZIP code based on bounding box size is then selected. Alternate splits of words are formed and the best split is selected in which the last formed group is detected to be the ZIP code.

Apparatus and method for separating handwritten characters by line and

A cellular processing system for analyzing an image comprising a matrix of points employs an image memory for storing digital data signals representative of each of the points, a plurality of special function processing units, each adapted to perform a specific operation on one or more images, and data bus means for selectively distributing image data from the image memory to one or more preselected function processors for processing in a cascaded fashion and returning the processed data signals back to image memory. The special function process units include a pipeline processor employing one or more programmable, substantially identical neighborhood transformation stages and an image combiner including means for performing arithmetic, logical, and conditional operations on one or more images.

High speed cellular processing system

Provision is made in a serial neighborhood transformation stage for generating statistical information relating to the number of transformations performed by the stage. This information can be transferred back to a host computer separately from the image pixels to indicate that there has been no change in the image being operated on by the stage or that a certain number of transformations have occured.

Image processing system with transformation detection

A system for analyzing images represented by a serial stream of digital electrical signals corresponding to values of pixels in a matrix of points constituting an image. The system includes a pipeline of substantially identical neighborhood transformation stages. Each stage includes a processor portion for analyzing the pixel values and a memory portion communicating with the processor portion for sequentially providing a window of neighboring pixels to the processor for analysis. A central programmable controller communicates with the pipeline over a single communication link which provides both the pixel value data to the pipeline and transformation control instructions to the processor portions of each stage. The memory portion preferably includes a random access memory which serves as a line storage device which may be readily adjusted to accommodate different raster scan line lengths from various image sensors. Each stage includes improved logic circuitry capable of performing a wide variety of analyses on both two-dimensional image data represented by binary pixel values and three-dimensional image data represented by multi-valued pixel values. Image border or off-image detection circuitry is also disclosed which is capable of detecting nonlinear boundaries for the image matrix.

Neighborhood transformation logic circuitry for an image analyzer system

A plurality of serial neighborhood transformation pipelines are provided for simultaneously operating on adjacent segments of a partitioned image matrix. Techniques are disclosed for bi-directionally transferring pixel data on the edges of adjoining segments of the image matrix between adjacent processors in a manner which minimizes the number of interconnections therebetween. In such manner a parallel pipeline image processing system can be implemented in integrated circuit form while keeping the number of pins for each stage in the pipeline to a minimum.

Parallel pipeline image processor

An image analyzer system includes a pipeline of individually programmable neighborhood transformation stages. Programming of the stages is accomplished by way of coded command signals which are either of a local or global type. Global commands propagate down the pipeline to all of the stages whereas local commands are utilized to program only selected stages. Once the stages are programmed the image data may be transferred over the same bus previously utilized to carry the programming instructions. In the preferred embodiment, control lines are employed to indicate whether image data or programming instructions are being transferred over the bus.

Image analyzer with common data/instruction bus

A system for analyzing images represented by a plurality of raster scan lines of pixel values employs at least one neighborhood transformation stage. The stage includes a processor portion for analyzing windows of neighboring pixel values and providing a transformation output as a function of the pixel values contained in the window. A random access memory (RAM) repetitively stores a given plurality of successive pixel scan lines fed to the stage. Selected pixel values from the RAM are loaded into the processor portion so as to sequentially access the neighborhood windows for analysis. The RAM serves as a recirculating line storage device for accommodating different raster scan line lengths.

Image analyzer with variable line storage

An image analyzer system employs one or more neighborhood transformation stages. The stage operates to access groups of neighboring pixels in an image matrix, analyzes them and generates a transformation output as a result of the analysis. The stage includes a logic circuit which is programmable from a central controller. In the preferred embodiment, each pixel in the neighborhood is analyzed by the logic circuit and temporarily stored until other pixels in the group have been analyzed. The combination of analyzed pixel values form the basis for generating the transformation output for the stage. Preferably, the logic circuit is designed to perform both two dimensional and three dimensional image analyses.

Growing community of inventors

Ann Arbor, MI, United States of America

David L McCubbrey