Hewlett-packard Company

David L McAllister

Michael R Diehl

Anthony C Barkans

Maynard Darvel Hammond

Robert B Manley

A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data. Once near-fullness occurs, low-address data in the buffer are overwritten with new data. In this manner, a traveling window to memory is provided. If the host system begins requesting data from an address region not covered by the window and such out-of-window requests result in a threshold number of buffer &ldquo;misses,&rdquo; then the system reinitializes itself. Upon reinitialization, the system effectively opens a new memory window corresponding to the new range of addresses being requested by the host system.

Hybrid cache/SIRO buffer system

A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor. Finally, the system includes a controller, responsive to the enable bit, configured to transfer data directly from the data transfer queue to the ancillary processor, the controller being operative to evaluate the at least one data ready bit and transfer the associated block of data from the queue to the ancillary processor if the at least one data ready bit indicates that the data is ready for transfer.

Method and apparatus for performing high speed data transfers between a

A color graphics pipeline has a separate encoder with a dither table for processing each color value in pixel data received from a host processor or rasterizer. The encoders modify color values and dither noise values and also combine both positive and negative dither noise values with the color values, for independent optimization of each color and for better edge detection in a color recovery filter within a decoder of the pipeline. Each encoder comprises the following elements. A comparator mechanism compares a color value with a predetermined cutoff value. A dither table provides dither noise values. An offset mechanism modifies the dither noise values to derive a modified dither noise value when the color value is greater than or equal to the predetermined cutoff value. An aliasing mechanism aliases the color value with other color values below the predetermined cutoff value to derive an aliased color value when the color value is less than the predetermined cutoff value. An adder mechanism adds the unmodified dither noise or modified dither noise to the aliased color value or nonaliased color value, respectively, to derive the dithered color value. A clamping mechanism ensures that the dithered color value resides within a predetermined color range. Finally, a quantizing mechanism quantizes the dithered color value to derive a quantized/dithered color value for storage in memory, such as in a frame buffer.

System and method for dithering and quantizing image data to optimize

A non-linear digital-to-analog converter (non-linear 'DAC') and method are disclosed for scaling a digital input value by a non-integer and producing an analog output. The digital input value is multiplied by a non-integer, and the integer portion of the result is fed to a linear DAC to produce a linear analog output. At least one of the bits of the integer portion of the result is decoded, and at least one compensation value is generated responsive to the decoding. The compensation value is added to the linear analog output and represents the fractional portion of the result of scaling the digital input value by the non-integer. A method is also disclosed for utilizing the non-linear DAC for error compensation in a computer graphics system. Color intensity values are scaled up by a non-integer greater than one. A first analog output is generated proportional to the integer portion of the result. At least one bit of the integer portion of the result is decoded, and a second analog output is generated responsive to the decoding. The second analog output represents the fractional portion of the result. The first and second analog outputs are combined, and the combined analog output is used to drive a display device.

Growing community of inventors

Fort Collins, CO, United States of America

David L McAllister