Data General Corporation

David L Keating

James Marriot Guyer

William F Baxter

David I Epstein

Robert G Gelinas

Joseph Cox

Tom V Radogna

Simon N Yeung

Art A Sherman

Pat J Weiler

Rob J Pike

Liz M Truebenbach

Doug J Tucker

Rob P Valentine

Phil J Roux

Andrea Heyda

Jeff S Kimmell

Michael F Hunt

Barry E Gillott

Dan R Huck

Michael Sporer

Mark Douglas Hummel

Steven J Wallach

Kenneth D Holberger

Steven Wallach

James B Stein

James E Veres

Harold R Kimmens

Wayne Colella

John Pilat

Micheal Sporer

Richard W Reeves

Steven M Staudaher

Walker Anderson

High availability computer system and methods related thereto

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Bus arbitration system for multiprocessor architecture

Symmetric multiprocessing computer with non-uniform memory access

A method and system for handling a branch instruction which requires branching from a current instruction of a first instruction sequence to the first instruction of a second instruction sequence. The branch instruction is fetched and the next instruction of the first sequence is fetched while the branch instruction is displacement formatted. The first instruction of the second sequence is fetched while such next instruction is displacement formatted and the branch instruction is executed. The second instruction of the second sequence is fetched while the first instruction is displacement formatted, but the next instruction of the first sequence is not executed so that an execution wait occurs. The third instruction of the second sequence is then fetched while the second instruction is displacement formatted and the first instruction is executed.

Unconditional wide branch instruction acceleration

A method is disclosed which enhances the ability of digital computer system to manage displays, especially in an environment where a single physical display supports a plurality of logical displays (windows). Machine-language instructions are provided which, in conjunction with user-supplied form descriptors describing each of the windows, enable management and generation of display image data to be performed directly by the processing hardware of the digital computer system, eliminating any need for intervening interpretive software. Data computed from form descriptors may be encached, enhancing the speed of consecutive operations on windows. Graceful creation is enhanced by permitting processing control to escape to software fault handlers.

Method of graphical manipulation in a potentially windowed display

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

Method and apparatus for enhancing the operation of a data processing

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

Data processing system with unique microcode control

A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.

Digital data processing system having dual-purpose scratchpad and

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.

Hierarchial memory ring protection system using comparisons of requested

Growing community of inventors

Holliston, MA, United States of America

David L Keating