S3 Incorporated, Inc.

Cypress Semiconductor Corporation

David L Hoff

Saroj Pathak

Nalini Ranjan

Sarathy Sribhashyam

Frederick S Chiu

A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays. Moreover, since the word line block, the data block, and the at least one memory cell are separate blocks, flexibility is provided in the placement of the blocks as each block requires a reduced amount of layout space as compared to all three blocks together. Also provided is a process using synthesis method for creating a digital electronic circuit with the memory architecture including the word line block, the data block, and the at least one memory cell.

Skew-independent memory architecture

A system for buffering input and output signals in a floating substrate technology environment comprises an output pre-driver and an output driver. The output pre-driver includes a pull-up subsystem and a pull-down subsystem, which both receive an output signal and an output enable signal. The pull-up subsystem includes a multistage delay circuit, a current regulation circuit, and a bootstrap circuit, a keeper circuit, an oscillator circuit, and a turn-off circuit, which are coupled together so that a pull-up signal is generated. The pull-down subsystem includes a stagger circuit and a switch circuit that are coupled together to generate a pull-down signal. The output driver includes a pull-up circuit to receive the pull-up signal and a staggered pull-down circuit to receive the pull-down signal. The output driver generates a pad signal used to drive a peripheral device that is coupled to the mixed voltage drive system. A method for a mixed voltage drive system for floating substrate technology is also disclosed.

System and method for a mixed voltage drive system for floating

A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.

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San Jose, CA, United States of America

David L Hoff