Xilinx, Inc.

David L Ferguson

Robert O Conn

Robert W Wells

Robert D Patrie

Daniel Y Chung

Gil A Speyer

Leo Kar Leung Poon

Rafael C Camarota

Khaldoon S Abugharbieh

Geoffrey A Richmond

Mustansir Fanaswalla

A characterization system includes a signal detector. The signal detector includes a first conversion unit configured to receive, from a first device, a first device output signal including N possible discrete pulse amplitudes and generate a plurality of detected signals based on a plurality of threshold amplitudes respectively. The signal detector further includes a second conversion unit configured to generate a first conversion output signal and a second conversion output signal based on logic values included in the plurality of detected signals and provide first and second conversion output signals to an analysis unit for generating one or more measurements of the first device. The first and second conversion output signals include Mand Mpossible discrete pulse amplitudes respectively. Mand Mare integers less than N.

System and method for device characterization

A transceiver circuit for self-test of jitter tolerance is disclosed. The transceiver circuit includes a transmitter circuit having an output coupled to an output terminal of the transceiver and a receiver circuit having in input coupled to an input terminal of the transceiver. The transceiver also includes a loopback path configured to provide a signal transmitted by the transmitter circuit to the input of the receiver circuit. The transceiver also includes a test control circuit that causes jitter to be introduced in the signal transmitted by the transmitter circuit when the test control circuit is operating in a self-test mode, but not when the test control circuit is operating in a non-test mode.

Circuit and method for testing jitter tolerance

A receiver circuit includes an analog front-end circuit, a first adaptation circuit, and a second adaptation circuit. A method operates the receiver circuit. The analog front-end circuit is configured to resolve an output signal from an input signal as a function of adjustable parameters. The first adaptation circuit is coupled to the analog front-end circuit and is configured to determine values of the adjustable parameters responsive to the output signal. The second adaptation circuit is coupled to the analog front-end circuit and to the first adaptation circuit. The second adaptation circuit is configured to adjust the values of the adjustable parameters responsive to one or more operating conditions of the receiver circuit. These operating conditions include a temperature and/or a power supply voltage of the receiver circuit.

Receiver circuit

A method of characterizing a die can include correlating, using a processor, a static voltage profile of a die under test in wafer form with a plurality of test static voltage profiles. The plurality of test static voltage profiles can be associated with dynamic performance profiles. The method further can include predicting dynamic performance of the die under test according to the dynamic performance profile associated with a test static voltage profile that is correlated with the static voltage profile.

Predicting performance of an integrated circuit

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Built-in self test using pulse generators

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

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Campbell, CA, United States of America

David L Ferguson