Advanced Micro Devices Corporation

Integrated Device Technology, Inc.

Other

Rogers Holster Co., LLC

David L Campbell

Jiu An

Steven Shyu

James E Fox, Jr

Jimmy Fung

William H Rogers

Matthew E McKendrick

Thomas H Templeton, Jr

Christopher P Wyland

Ravindra D Tembhekar

Kanoosh Naghshineh

Magazine block device for firearm dry fire practice which allows a user to practice proper firearm handling skills without expending ammunition, including recocking and actuating the firearm slide without pressing the slide lock release. In an aspect, a magazine block device is provided having a bullet-shaped body, two upper ridges forming a longitudinal channel through which the firearm breach face loading tab may pass without dislodging the magazine block device, and an offset lower ridge. The lower ridge is configured to evenly force a magazine follower down a sufficient distance to prevent actuation of the firearm slide lock. This allows dry fire practice of pulling the slide. Several other features include ridges to assist a user to remove and load the block device in and out of a magazine, as well as a pocket to mechanically remove same.

Magazine block for dry fire practice

An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for controlling the voltage of the bulk region, a resistive element and a gate drive control circuit are also formed in the silicon substrate. A layer of interconnect formed over a top surface of the silicon substrate may selectively couple into the output driver circuit one or more of the resistive element between a source of the pull-down output transistor and a reference voltage source, the bulk potential control circuit to control the voltage of the bulk region of the silicon substrate, and the gate drive control circuit to control the rate of change of voltage on the gate of the pull-down transistor as a function of the voltage on this gate.

Method and structure for selectively coupling a resistive element, a

A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.5 nanosecond existing between the squarewave signals on the output terminals.

Logic gate with controllable hysteresis and high frequency voltage

An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line. In another aspect of the invention, the output driver circuit comprises a bulk potential control circuit which changes the voltage of the semiconductor bulk in which the pullup FET is disposed. Accordingly, bounce on the voltage supply lines is minimized, propagation delay through the output driver is minimized, and the output driver is suitable for use in applications requiring the handling of live insertion.

Output driver circuits with enhanced supply-line bounce control and

A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground). The leadframe is formed from a single sheet of material by, for instance, stamping or etching. The leadframe may be used in either ceramic or plastic packages. The leadframe reduces switching noise and crosstalk, allows more flexibility in placement of power and/or ground bond pads on the die, and allows provision of ground and power planes in an integrated circuit package that is thinner than previous integrated circuit packages containing both ground and power planes.

Leadframe with power and ground planes

In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

Switchable DAC with current surge protection

A pipeline memory access circuit has a memory address buffer for buffering memory addresses. The buffer has a first and a second pass gate, and each of the pass gates has a pair of complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided for selectively switching the buffer between an asynchronous and a synchronous mode of operation. The switching apparatus includes circuits for alternately opening and closing the first and second pass gates when the buffer is in its synchronous mode of operation and for simultaneously opening both of the pass gates when the buffer is in its asynchronous mode of operation.

Asynchronous/synchronous pipeline dual mode memory access circuit and

In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse bias potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

An ECL bandgap reference voltage generator includes a supply-independent current source (14) to produce an output reference voltage (V.sub.BB) that is independent of variations of supply voltage but yet without consuming additional power dissipation. The supply-independent current source (14) is formed of a pair of transistors (Q907, Q908) and first through third resistors (R903, R904, R908).

Temperature and supply compensated ECL bandgap reference voltage

Method and apparatus suitable for inclusion in an integrated circuit transceiver meeting IEEE 802.3 standards which detects 'collisions' so that more than one station will not simultaneously transmit over a network. The method employs a novel three-pole cyclical low-pass filter which attenuates the ac component received over the network to less than 20 mV to allow collision detection within the 900 nanosecond budget allowed by the IEEE standard. A differential operational amplifier receives the signal from the network and a collision reference voltage. The signal generated by the differential amplifier is filtered by the low-pass filter and then coupled to a high-gain comparator which acts as a zero-crossing detector. The comparator generates ECL logic signals representing the occurrence or non-occurrence of a collision. The resulting collision detector operates over a wide range without the need for field 'trimming'.

Detection of direct current in the presence of manchester-encoded signals

An operational amplifier suitable for inclusion in an integrated circuit device operating as a transceiver at a coaxial media interface to a network meeting IEEE 802.3 standards. To be included in an integrated circuit package the operational amplifier must have low-power consumption and yet generate up to 80 mA of current onto the network. A design method achieves this goal, producing an operational amplifier having three independently-positioned, isolated, poles. A current generator and level shifter is employed with the operational amplifier which generates a current precisely proportional to a 'collision' reference voltage, the current is compensated for changes in temperature and for variations in transistor gain (hFE). A very wide band level shifter matches the current generated to the requirements of the operational amplifier so that 10% to 90% changes in current generated by the op amp can occur in 1/2 to 3/4 of a nanosecond, yet the level shifter does not consume much power. The current generator provides a single point of circuit element control for compensating for hFE variation in three transistors used within the current generator. The level shifter employs current-steering to produce the switched current which is exceptionally fast and low in asymmetry. The process used in integrated circuit manufacture permits tight control of the elements within the operational amplifier so that parameters can be held within 2% of the tolerances specified in the IEEE 802.3 standards without need of field 'trimming'.

High-current operational amplifier

A master-slave flip-flop device wherein the master segment employs function and load isolated outputs driven in parallel with cross-coupled latch transistors is described. Signal feed forward may also be provided from a similarly isolated output of the master segment to a device output gate which also receives the otherwise final output of the slave segment. The device is found to exhibit a minimized duration of the undesired metastable state of the master segment and to, thereby, enhance propagation speed in which a stable state is established.

Master-slave multivibrator with improved metastable response

The fall-time of an ECL gate is precisely controlled using a fixed capacitor, which is connected between the positive supply voltage and the ECL gate output terminal, and a variable current source connected between ground and the ECL gate output terminal. A time-delay circuit is obtained by controlling the variable current source with an error voltage of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates with controlled fall-times in a ring oscillator configuration. Addition of a non-inverting input to one ECL gate makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided by phase-locking the output signal of a first phase-locked loop to a system reference signal to generate a first-loop control voltage. A second phase-locked loop is phase-locked to the received signal with a second-loop control voltage. In addition, the second phase-locked loop is also frequency-locked to the system reference signal by the first-loop control voltage. This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

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Sunnyvale, CA, United States of America

David L Campbell