Digital Equipment Corporation

David L Brash

Neal Andrew Crook

Michael J Seaman

John M Lenthall

A queue based arbiter to arbitrate between N devices of a computer system for access to a system bus which eliminates the need to maintain a history of bus transactions by queuing bus requests to track when a bus request is posted. The arbiter provides fair access to the bus by maintaining a queue of requests that come in from each resource in the computer system. This is accomplished by continually sampling the individual request lines of the devices to determine if a device is requesting access to the bus. Each time the arbiter detects a request from a device it puts an entry representative of the specific device that has requested the bus into a queue that has at least N entries. Requests are granted in the order that they are queued.

Queue based arbitration using a FIFO data structure

A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.

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Reading, United Kingdom

David L Brash