Hong Kong Applied Science and Technology Research Institute Company, Limited

David Kwok Kuen Kwong

Kam Chuen Wan

Yat To Wong

Chik Wai Ng

Chun Fai Wong

Ho Ming Karen Wan

Chit Ah Mak

Xiaofei Kuang

Jennifer Shuet Yan Ho

David Chik Wai Ng

Lap Chi Leung

A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.

Feedback controller having multiple feedback paths

A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

Gain control circuit

Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

Low voltage synchronous oscillator for DC-DC converter

The fuse cell architecturefor the presently claimed invention employs a multiple fuse structurearchitecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structurespossessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell

Fuse cell and method for programming the same

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Davis, CA, United States of America

David Kwok Kuen Kwong