Silego Technology Inc.

David Kuneth Chow

Vikas Vinayak

Nathan Willis John

Sidney Chan

A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.

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San Jose, CA, United States of America

David Kuneth Chow