Psemi Corporation

Peregrine Semiconductor Corporation

Murata Manufacturing Co., Ltd.

David Kovac

Dan William Nobbe

Tero Tapio Ranta

Joseph P Golat

Chris Olson

Jeffrey A Dykstra

Kelly Michael Mekechuk

Robert Mark Englekirk

Ronald Eugene Reedy

Keith Bargroff

Eric S Shapiro

Christopher C Murphy

Michael P Gaynor

Jonathan James Klaren

David Halchin

Gary Frederick Kaatz

Cheryl V Liss

Joseph Golat

Poojan Wagh

Emre Ayranci

Parvez Daruwalla

Erica Poole

Neil Calanca

Dan Willaim Nobbe

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

Cascode gain boosting and linear gain control using gate resistor

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Methods and apparatuses for use in tuning reactance in a circuit device

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Cascode amplifier bias circuits

Methods and devices for reducing coupling of RF frequency components between different bands of an RF system are presented. According to one aspect, a notch filter having a notch centered at a harmonic of a fundamental frequency of a first band transmit side is coupled to an output of an LNA of the first band. According to another aspect, the harmonic is a second harmonic, a third harmonic or higher order harmonics. According to another aspect, the notch filter includes a plurality of notches at respective plurality of harmonics. According to a further aspect, the notch has an attenuation of 30 dB or greater at the second harmonic and 10 dB or greater at the third harmonic. Further included is a method for reducing coupling of harmonics of signals transmitted in the first band into a receive path of the second band, thereby increasing noise figure/sensitivity performances of the receive path.

LNA with Tx harmonic filter

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a 'common source' configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

Source switch split LNA design with thin cascodes and high supply voltage

Methods and apparatuses for providing a tunable Wilkinson power splitter are presented. According to one aspect, the tunable splitter includes tunable branches realized via lumped elements that provide controlled impedance and phase at different selectable center frequencies of operation. For each of the center frequencies, the tunable Wilkinson splitter has a performance according to a corresponding fixed center frequency Wilkinson power splitter provided by a relatively narrow instantaneous bandwidth. Over a number of the center frequencies supported, performances of the tunable Wilkinson splitter overlap to provide a combined performance having a desired wider bandwidth. According to another aspect, each of the tunable branches includes an LC network that includes tunable capacitors and inductors. One or more of the tunable Wilkinson power splitters can be cascaded to provide a performance according to a wider instantaneous bandwidth.

Tunable Wilkinson splitter

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Switch capacitance cancellation circuit

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Scalable periphery tunable matching power amplifier

RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.

High power RF switch with controlled well voltage for improved linearity

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a 'common source' configured input FET and a 'common gate' configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

Growing community of inventors

Arlington Heights, IL, United States of America

David Kovac