Arm Limited

David Kevin Hart

Andrew Christopher Rose

Michael John Williams

Andrew Brookfield Swaine

Vladimir Vasekin

Andrew Burdass

Patrick Gerard McGlew

Javed Osmany

A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

Generation of trace data in a multi-processor system

A data processing apparatus having a plurality of memories is provided in which address generation logic () outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logic () outputs a prediction indicating in which one of the plurality of memories a target data is stored. The target memory prediction logic () outputs the prediction in the same processing cycle as the output of the target memory address by the address generation logic (). An associated method is also provided.

Data access target predictions in a data processing system

A cache memory includes error bits corresponding to each line of data. An error detecting circuit uses these error bits to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.

Error correction within a cache memory

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Cambridge, United Kingdom

David Kevin Hart