Dell Products Inc.

David Keith Chalfant

Swamy Kadaba Chaluvaiah

Vaideeswaran Ganesan

Suren Kumar

B Balaji Singh

Tuyet-Huong Thi Nguyen

Jordan Chin

Jose M Grande

Krishnaprasad Koladi

Scott Michael Ramsey

Wei Liu

PoYu Cheng

Tzu-Hsiu Tsai

Swamy Kadaba

Jagadeesha Bollandoor

Yaohui Hung

Yiping Zhou

A hybrid firmware-first/operating-system-first error handling system includes a Basic Input/Output System (BIOS) subsystem coupled to a processing system. The BIOS subsystem begins an initialization process for a computing device and, in response, configures the processing system to perform processing system firmware-first error handling operations and, for any errors that are detected during at least a portion of the initialization process, performs BIOS firmware-first error handling operations. During the initialization process, the BIOS subsystem determines that an operating system provided by the processing system is configured to perform error handling and, in response, disables the performance of processing system firmware-first error handling operations by the processing system, and instructs the operating system to perform operating-system-first error handling operations such that the operating system performs the operating-system-first error handling operations for any errors that are detected during runtime of the computing device.

Hybrid firmware-first/operating-system-first error handling system

An information handling system includes multiple PCIe devices and a basic input/output system (BIOS). The BIOS receive a system management interrupt (SMI). The SMI is in response to a detection of an error on a first PCIe device of the PCIe devices. The BIOS collect data associated with the first PCIe device. The data includes a friendly full device description for the first PCIe device. Based on the friendly full device description, the BIOS determine a friendly name for the PCIe device. The BIOS provide an error message on a display device of the information handling system. The error message includes a type of the error detected and the friendly name for the PCIe device.

Reporting PCIe device error information

Controlling access to an ERST, including: triggering, in response to an occurrence of an error, a SMI; adjusting, in response to the SMI and by a SMM RAS handler module, a slate of an access gate from a locked state to an unlocked state, the access gate controlling access to an ERST storage region; generating, by an OS MCE handler, an error record based on the error; accessing, by the OS MCE handler, an ACPI ERST to identify instructions for storing the error record at the ERST storage region; triggering, in response to the instructions and by the OS MCE handler, an additional SMI; determining, in response to the additional SMI and by a SMM handler, that the access gate is in the unlocked state; in response to determining that the access gate is in the unlocked state: storing, by the SMM handler, the error record at the ERST.

Controlling access to an error record serialization table of an information handlng system

An information handling system includes a processor and a basic input/output system (BIOS). The processor executes an operating system, and detects a corrected error from a memory controller of the information handling system. In response, the processor generates a system management interrupt (SMI). In response to the SMI the BIOS executes a SMI handler. The SMI handler detects a row of the corrected error within a dual inline memory module (DIMM) of the information handling system, and determines whether an entry for the row is located within a hash table. In response to the entry for the row being located within the hash table, the SMI handler increments an error count in a field of the entry for the row. Otherwise, the SMI handler adds a new entry for the row to the hash table, and increments an error count in a field of the new entry for the row.

System and method for tracking memory corrected errors by frequency of occurrence while reducing dynamic memory allocation

An information handling system may perform a quick boot based on a determination that a boot does not require an update to at least one of a firmware and hardware of an information handling system. The information handling system may reboot and may determine whether a boot of the system requires an update to at least one of a firmware and hardware of the information handling system. If the boot does not require an update to the at least one of a firmware and hardware of the information handling system, the information handling system may boot by bypassing one or more basic input/output system (BIOS) power-on self-test (POST) operations.

Information handling system quick boot

An information handling system may reset components logged in a memory of the information handling system. For example, an information handling system may determine components logged in an information handling system memory and may perform a bulk reset of the logged components.

Information handling system adaptive component reset

A baseboard management controller (BMC) of an information handling system may notify an operating system of the information handling system of receipt of a firmware update for a PCI component. The operating system of an information handling system may receive a notification from a BMC of the information handling system, via a basic input/output system (BIOS), of the information handling system that the BMC has received the firmware update. The operating system may halt traffic to the PCI component for which an update has been received, and the update may be applied to the component.

Component firmware update from baseboard management controller

A baseboard management controller (BMC) of an information handling system may generate a signal to cause the information handling system to reload a kernel of an operating system of the information handling system. The BMC may generate a signal for reloading a kernel of an operating system of an information handling system, and the information handling system may reload the operating system kernel.

Kernel reset to recover from operating system errors

A processor memory mapped boot system includes a processing system having a processor memory subsystem, and a memory system having at least one memory device. A Basic Input/Output System (BIOS) engine is coupled to the processing system and the memory system, and is configured to begin boot operations and detect a boot memory mode setting for the processor memory subsystem. The BIOS engine configures a memory space that includes the at least one memory device and the processor memory subsystem. In response to detecting the boot memory mode setting, the BIOS engine will configured the processor memory subsystem to provide a first memory region of the memory space. The BIOS engine will then complete boot operations utilizing the processor memory subsystem providing the first memory region of the memory space.

Processor memory mapped boot system

Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

Systems and methods to prevent system crashes due to link failure in memory mirroring mode

An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.

System and method for BIOS to ensure UCNA errors are available for correlation

An information handling system includes a dynamic random access memory, and a processor. The dynamic random access memory includes a lower memory portion and multi-channel dynamic random access memory portion. The dynamic random access memory is allocated to operations of a boot process of the information handling system. The processor communicates with the dynamic random access memory. The processor determines whether a fast memory allocation service is detected in the boot process. In response to the fast memory allocation being detected, the processor allocates the multi-channel dynamic random access memory portion of the dynamic random access memory to operations of the boot process.

System and method to allocate available high bandwidth memory to UEFI pool services

An on-package multi-channel dynamic random access memory stores data associated with write requests. An off-package memory stores a copy of the data associated with the write requests. A resiliency driver detects a write request, stores data for the write request to the on-package multi-channel dynamic random access memory as a primary image, stores a backup of the data for the write request to the off-package memory as a secondary image, detects a read request, and reads data for the read request from the on-package multi-channel dynamic random access memory as the primary image.

System and method for memory fault resiliency in a server using multi-channel dynamic random access memory

An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.

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Round Rock, TX, United States of America

David Keith Chalfant