Altera Corporation

David Karchmer

Stephen D Brown

Terry Borer

Gabriel Quan

Andrew Leaver

Daniel S Stellenberg

Michael David Hutton

Vaughn Betz

Jason Govig

Ryan Fung

Francis B Heile

Jim Park

James G Schleicher, Ii

Mihail Iotov

Marwan A Khalaf

Jimmy Lawson

James G Schleicher

Jinyong Yuan

Babette Van Antwerpen

Alan Louis Herrmann

David Neto

Kumara Tharmalingam

Kevin Chan

Brent Alan Fairbanks

Erhard Joachim Pistorius

Scott D Redman

Pouyan Djahani

Zhiru Zhang

Tamlyn V Rawls

William Buckner Davis

Jeffrey Chen

A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

Method and apparatus for performing compilation using multiple design flows

M/A for performing incremental compilation using top-down and bottom-up design approaches

A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.

Method and apparatus for performing path-level skew optimization and analysis for a logic design

A method or apparatus that allows new devices to be easily integrated with computer aided design (CAD) tools via an easily extensible application programming interface (API). In an embodiment, new devices are added by reading a new device type and assigning a sequential index value. Index values are assigned to the new devices by appending a new device type to the end of an enumeration construct. When the data structure is compiled, the new device type is converted to a sequential index value. Data values for the new device are added to a data structure and can be accessed via the index value. Because the added device type is appended to the end of the enumeration construct, the index values assigned to the original data types remain unchanged. Consequently, recompilation is only required for applications that need to access the new devices and is unnecessary for the applications that do not use the new devices.

Method for adding device information by extending an application programming interface

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.

Method and apparatus for comparing programmable logic device configurations

A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation phases. The user design is parameterized. The performance estimation model outputs a probability distribution function of estimated performance values of the user design, based upon this parameterization. The performance estimation model is created by parameterizing sample designs. The sample designs are compiled and analyzed to determine their performance values. To account for random variability in compilation phases, the module compiles and analyzes sample designs multiple times. The performance estimation model is created from the relationship between sample designs' performance values and their parameterizations. A regression analysis may be used to determine this relationship. The performance estimation model can be updated with the analysis of compiled user designs. The performance values can include timing, power, and resource consumption.

Early timing estimation of timing statistical properties of placement

During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.

Method and apparatus for compiling programmable logic device configurations

Compiler flows are provided that can produce functionally equivalent field programmable gate arrays ('FPGAs') and structured application-specific integrated circuits ('structured ASICs'). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.

Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits

A visualization displays user designs and performance information at different levels of detail. Related register bits are combined into a metaregister and displayed as a graph node. The set of paths and associated combinatorial logic between two or more metaregisters are collapsed into a metapath and displayed as a graph connection. The set of paths associated with a metapath can be selectively revealed in response to user input. Metapaths can be annotated with performance information of its associated paths, such as timing, area, and power consumption information. The annotated performance information can represent performance information of one or more paths or aggregate attributes of the set of paths. Paths associated with control signals and finite state machines can be identified and displayed as separate graph connections.

Performance visualization system

A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. Chunks are identified from the domains and sub-domain. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Method and apparatus for performing parallel slack computation

Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques. Portions of the design may be designated as critical with respect to timing, area, power consumption or any other performance aspect.

User-directed timing-driven synthesis

The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while preserving the original clock domain relationship of the edges in the path. To that end, the method includes generating a timing graph having a source instance, a destination instance and a plurality of edges defining a plurality of signal paths between the source instance and the destination instance. A plurality of clock domains is corresponded to the timing graph, with a subset of the plurality of edges being associated with more than one clock domain. From the subset, conflicting clock domains associated with a common edge are identified. In response to identification of the conflict, one of the clock domains is dissociated from one of the edges of the subset.

Clock domain conflict analysis for timing graphs

Growing community of inventors

Los Altos, CA, United States of America

David Karchmer