Intel Corporation

David K Vavro

Kumar S Golla

James Mitchell

Tinku Acharya

Edward A Pazmino

James A Mitchell

A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. Each of these processors may also accomplish math functions when input and output processing is not necessary. The various processors may communicate with one another through general purpose registers which receive data and provide data to any of the processors in the system. Math processors may be added as needed to accomplish desired mathematical functions. In addition, a RAM processor may be utilized to hold the results of intermediate calculations in one embodiment of the present invention. In this way, an adaptable and scaleable design may be implemented that accommodates a variety of different operations without requiring redesign of all the components.

Digital signal processor having a plurality of independent dedicated processors

Digital signals processor having a plurality of independent dedicated processors

Embodiments of the invention provide an instruction that computes the horizontal and vertical values (H,V) based upon the predefined equations. Based upon the horizontal and vertical values (H,V) and the current sign bit being processed at [m,n], the output context and decision pair (CX,D) is determined placed into a destination register.

Sign coding and decoding

A method and apparatus for accelerating the conversion and detecting image data in pixel format into bit-plane format and bit plane format to pixel format for JPEG2000 compression and decompression is disclosed. In one embodiment, a method for encoding coefficients comprises applying one or more wavelet transforms to generate multiple coefficients, converting the pixel coefficients into bit-plane format and detecting zero bit-planes. This causes the image data in pixel to be broken into bit planes and stored in memory. If all the bits in a selected pixel plane are zero, an indication is stored in an N bit memory array corresponding to the N bit planes of the pixel code block that is processed. The indicator bits are useful in speeding up further compression.

Bit-plane formatting including zero bit-plane detection

Embodiments of the invention provide a run length coding instruction for determining output context and decision values. Pixel coefficient bit values are used after wavelet transformation to determine output context (CX) and decision (D) values. The input is comprised of coefficient bit values (bit, bit, bit, bit) in accordance with the scan order and the output are CX and D values. The CX and D pairs are processed together by arithmetic encoder to produce compressed data output (CD). CX selects the probability estimate to use during the coding of D.

Run length coding and decoding

Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with a predefined modes of indexing. The counters support slipping when counting to support convolutional filters in one-dimension (1D) and two-dimension (2D). For 2D indexing, a first counter indexes in the X direction and a second counter indexes in the Y direction in memory. The values from the first and second counter are combined with an offset value to form an address directly to memory.

Multimedia address generator

A digital signal processor may include a plurality of processing elements that are coupled together to accomplish a specialized function. Each processing element may utilize the same shared storage in a form of a plurality of general purpose registers. Each of these registers may be accessed by any of the processing elements. Each register may include a data storage section and a plurality of storage areas for data valid bits that indicate whether the data is valid or not for each of the plurality of processing elements.

Different register data indicators for each of a plurality of central processing units

When encoding and decoding bit planes, a decision is made in the clean up pass if zero coding or run length coding should be performed. Embodiments of the invention provide a zero coding or run length coding decision instruction. The instruction will determine whether significance state variables associated with selected coefficients bits and their immediate neighbors are zero. If all the significance states are determined to be zero, then run length coding is performed. Else, zero coding is performed.

Zero length or run length coding decision

According to one embodiment, a processing element is disclosed. The processing element includes an instruction buffer, a first most often (MO) buffer coupled to the instruction buffer and an execution unit coupled to the instruction buffer and the first MO buffer. The execution unit is adaptable to execute instructions stored within the first MO buffer based upon a first predetermined profile.

Method for memory optimization in a digital signal processor

An apparatus to perform symmetric filtering image compression is provided. The apparatus includes an N-element shift circuit, that has N shifting blocks (SB), to store and shift data elements. Each data element represents a pixel of an image. The apparatus also includes a first plurality of adder circuits to add data elements from a first plurality of pairs of SBs of the N SBs. The apparatus further includes a second plurality of adder circuits to add data elements from a second plurality of pairs of SBs of the N SBs. Additionally, the apparatus includes a first plurality of multiplier circuits, to multiply by corresponding low pass coefficients results of additions performed by the first plurality of adder circuits. The apparatus also includes a second plurality of multiplier circuits, to multiply by corresponding high pass coefficients results of additions performed by the second plurality of adder circuits.

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Chandler, AZ, United States of America

David K Vavro