Harris Corporation

United States of America As Represented by the Secretary of the Air Force

Rockwell International Corporation

David K Vail, Jr

Michael J Iacoponi

David F Seefeldt

Stephen S Wilson

John W Murphy

Mark D Fisher

A 'just in time' pipelined signal processing architecture for a phased array antenna simultaneously updates the weights of all phase control elements of the antenna with reduced wiring complexity and fast beam steering updates. Signal propagation paths between a pipelined communication link--through subarray control processors distributed along the pipeline link--and phase control elements of the antenna array are provided with respectively different serial pipelined transport delays. These delays are such that all phase control signals produced by the subarray control processors are applied simultaneously to their associated subsets of antenna phase control elements. The use of serial (FIFO) delays to equalize pipeline and weight processing latency allows each subarray controller to process and forward serial beam vector data at the same data rate at which it is received from an upstream host processor.

Serial pipelined phase weight generator for phased array antenna having

A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern. Prescribed ones of the gate supercells and input/output supercells within at least one prescribed portion of the array are interconnected to effectively form an integrated circuit architecture capable of implementing the prescribed signal processing function. This portion is then separated from the wafer, and the integrated circuit architecture resident in the separated portion of the array is tab bonded to signal coupling terminals of an integrated circuit chip carrier by way of bonding pads on the input/output supercells.

Hierarchical variable die size gate array architecture

A high-resolution digital pulse to digital pulse divider circuit directly synthesizes precise frequencies having low phase noise content and phase continuity when frequency changes occur.

Digital frequency synthesizer circuit

An electronic time-of-day clock having a low-power time source and compensation circuits selectively operable responsive to pulses output from the low-power time source when system primary power is off or disabled, and responsive to a relatively highly accurate time-pulse generator when primary power is enabled. The time-of-day clock compensates continuously in real-time for errors in the output of the low-power time source caused by variations in the ambient temperature of the device; when primary power is enabled, the output of the low-power time source is further compensated by comparing the output thereof with the output of the high-accuracy frequency standard and storing accumulated error.

Growing community of inventors

Palm Bay, FL, United States of America

David K Vail, Jr