Intel Corporation

Kuck & Associates, Inc.

David K Poulsen

Sanjiv M Shah

Hong Wang

Gautham N Chinya

Richard A Hankins

Baiju V Patel

John Thomas Shen

Paul M Petersen

Ryan N Rakvic

Ed Grochowski

Murali M Annavaram

Shirish Aundhe

Jason W Brandt

Per H Hammarlund

Scott Dion Rodgers

Prashant Sethi

Shivnandan D Kaushik

Bryant E Bigbee

Xiang Chris Zou

John P Shen

James Paul Held

Douglas M Carmean

Alexander V Supalov

William R Magro

John L Reid

James Charles Abel

Grant E Haab

Andrey B Derbunovich

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Load balancing for multi-threaded applications via asymmetric power throttling

Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-managed thread unit (proxy) to invoke the OS-provided structured exception handling service (including dispatcher) on behalf of the sequestered thread unit. Alternatively, an OS-managed thread unit may include dispatch code and may, without OS intervention, dispatch the filter routine to the sequestered thread unit. Other embodiments are also described and claimed.

Structured exception handling for application-managed thread units

Data structure creation, organization and management techniques for data local to user-level threads are provided. In one embodiment, a method includes generating, for a user-level thread ('shred') to run on a thread unit that is not managed by an operating system ('OS'), a storage area for local data and maintaining state in the storage area across a context switch from the thread unit that is not managed by the OS to a second thread unit that is managed by the OS. Other embodiments are also described and claimed.

Data structure and management techniques for local user-level thread data

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Sequencer address management

A message passing interface ('MPI') cluster may be initialized and configured by reading a list of node identifiers from a file, starting a process on each node whose identifier was listed, and providing a second list of node identifiers to the process.

Method and apparatus for transparent selection of alternate network interfaces in a message passing interface ('MPI') implementation

A method and apparatus for a atomic operation is described. A method comprises receiving a first program unit in a parallel computing environment, the first program unit including a memory update operation to be performed atomically, the memory update operation having an operand, the operand being of a data-type and of a data size, and translating the first program unit into a second program unit, the second program unit to associate the memory update operation with a set of one or more low-level instructions upon determining that the data size of the operand is supported by the set of low-level instructions, the set of low-level instructions to ensure atomicity of the memory update operation.

Method and apparatus for an atomic operation in a parallel computing environment

A software-implemented method for validating the correctness of parallel computer programs, written in various programming languages, with respect to these programs' corresponding sequential computer programs. Validation detects errors that could cause parallel computer programs to behave incorrectly or to produce incorrect results, and is accomplished by transforming these parallel computer programs under the control of a general purpose computer and sequentially executing the resulting transformed programs. The validation method is system-independent and is portable across various computer architectures and platforms since validation is accomplished via program transformation; thus, the method does not depend on the features of a particular hardware architecture or configuration, operating system, compiler, linker, or thread environment. The input to the validation method is a parallel computer program. The parallel computer program results from annotating its corresponding sequential computer program with a parallelism specification; the annotations describe constraints in the sequential program to be relaxed to allow the exploitation of parallelism. Validation is accomplished by detecting semantic inconsistencies between the parallel computer program and its corresponding sequential computer program. The validation method translates the input parallel computer program into a second, sequential computer program such that the second sequential computer program, when executed, detects and reports the semantic inconsistencies between the parallel computer program and its corresponding sequential computer program.

Software implemented method for automatically validating the correctness of parallel computer programs

A software-implemented method for dynamically and statically privatizing global storage objects in parallel computer programs written in various programming languages. Privatization is accomplished via transformation of these parallel computer programs under the control of a general purpose computer. The privatization method is system-independent and is portable across various computer architectures and platforms since privatization is accomplished via program transformation; thus, the method does not depend on the features of a particular hardware architecture or configuration, operating system, compiler, linker, or thread environment. The inputs to the method are a parallel computer program, comprising parallel regions of execution and global storage objects, and a privatization specification describing the global storage objects to be privatized and the particular parallel regions, and manner, in which each of these objects is to be privatized. The privatization method itself translates the input parallel computer program into a second parallel computer program, according to the privatization specification, such that the second parallel computer program, when executed, accesses the specified global storage objects in a privatized manner, without requiring any explicit programmer modifications to the input parallel computer program.

Software implemented method for thread-privatizing user-specified global

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Champaign, IL, United States of America

David K Poulsen