Digital Equipment Corporation

David K Morgan

Barry A Maskas

Jesse B Lipcon

In a memory module, signature data identifying the configuration of memory in that module is multiplexed onto a general memory data bus along with memory data normally transferred during memory access operations. A plurality of such memory modules can be combined in an automatic sizing memory system using a configuration status register to store configuration data for each of the memory modules. The configuration status register can include several independent status registers, each corresponding to a different memory module. Each of the status registers can contain a base address identifying the starting address of each of the modules. Elements in the configuration status register can then compare the addresses received from a central processor unit to the base address data in each of the status registers to select the memory module containing the location corresponding to each address.

Automatic sizing memory system with multiplexed configuration signals at

In a memory module, signature data identifying the configuration of memory in that module is multiplexed onto a general memory data bus along with memory data normally transferred during memory access operations. A plurality of such memory modules can be combined in an automatic sizing memory system using a configuration status register to store configuration data for each of the memory modules. The configuration status register can include several independent status registers, each corresponding to a different memory module. Each of the status registers can contain a base address identifying the starting address of each of the modules. Elements in the configuration status register can then compare the addresses received from a central processor unit to the base address data in each of the status registers to select the memory module containing the location corresponding to each address. The status register can also contain validity and error indicators.

A self-testing memory simultaneously writes test patterns into the memory banks of the memory, simultaneously compares the contents of one of the memory banks with the contents of the other of the banks, and records errors when the contents of the one memory bank differ from the contents of the other banks.

Self-testing memory

A circuit implemented in CMOS technology that controls the rise and fall times of signals applied to conducting paths of a printed circuit board. The circuit consists of an input inverter circuit stage that controls the slope of an output signal from the inverter stage produced in response to an input signal. A second stage is implemented as a source follower and, in response to the inverter stage output signal, provides the output signal applied to the conducting paths of the printed circuit board. A final stage of the circuit compensates for the inability of the source follower stage to utilize, because of the characteristics of the CMOS field effect transistors, the range of voltages provided by the power supplies. The circuit, by controlling the rise and fall time of signal applied to the printed circuit board, reduces the ringing (i.e. the signal undershoot or overshoot) that can accompany application of pulsed signals to the printed circuit board.

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Hopkinton, MA, United States of America

David K Morgan