Advanced Micro Devices Corporation

Texas Instruments Corporation

Programmable Silicon Solutions

Other

Amic Technology Corporation

David K Liu

Ting-Wah Wong

Chi K Chang

Kueing-Long Chen

Man Wong

Cetin Kaya

Ming Sang Kwan

Kou-Su Chen

Wenchi Ting

Jian Feng Chen

Sameer S Haddad

Yu Nan Sun

Jian Chen

Yuan Tang

Bert R Riemenschneider

Mark T Ramsbey

Michael Allen Van Buskirk

Lee Edward Cleveland

Howard L Tigelaar

Hao Fang

Shane Charles Hollmer

James Juen Hsu

Ashwin H Shah

Nader A Radjy

Ming-Sang Kwan

Kelvin Yupak Hui

Cheing-Long Chen

Shengwen Luan

An integrated circuit die include a first portion including logic circuits. A second portion of the die includes an EEPROM memory, and a third portion includes a FLASH memory.

Device with embedded flash and EEPROM memories

A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

Method of forming a memory cell

Memory cell having implanted region formed between select and sense

A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

Flash memory cell and a new method for sensing the content of the new

Nonvolatile memory

A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.

Compact nonvolatile memory

A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Circuit and method for erasing flash memory array

A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first polysilicon layer as a floating poly in a predetermined number of transistors of the plurality of transistors in the periphery region, and forming a second polysilicon layer as a common gate line in the plurality of transistors, wherein the predetermined number of transistors prevent breakdown of the plurality of transistors below a predetermined field threshold voltage. In one aspect, the field oxide layer has a thickness of about 2500 angstroms. A plurality of transistors formed in a substrate of a periphery region of a Flash EPROM semiconductor circuit includes a first predetermined number of periphery transistors having a floating poly and a common gate line, and a second predetermined number of periphery transistors having the common gate line and adjacent the first predetermined number of transistors, the first predetermined number of transistors preventing breakdown of the second predetermined number of periphery transistors below a predetermined field threshold voltage.

Method and semiconductor circuit for maintaining integrity of field

A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.

Circuit for detecting both charge gain and charge loss properties in a

The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.

Highly scalable FLASH EEPROM cell

A plurality of transistors according to the present invention formed on a semiconductor wafer including a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.

Semiconductor circuit including non-ESD transistors with reduced

A gate stack formation process directed toward reducing floating gate oxidation which influences tunnel oxide thickness and, therefore, discharge speed. On a substrate upon which is formed an oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer, only the second polysilicon layer and dielectric layer are etched. Source and drain regions are implanted through the first polysilicon layer. Subsequently, the first polysilicon layer is etched to form the full gate stack.

Method of eliminating or reducing poly1 oxidation at stacked gate edge

Growing community of inventors

Cupertino, CA, United States of America

David K Liu