Motorola Corporation

David K Ford

Bernard E Weir, Iii

Paul J Moller

Phuc C Pham

Patrick J Marry

Philip Alan Jeffery

Dennis Joe Cashen

Douglas W Main

Rafaele Pini

Daniel E Kobylarz

Phil Jeffery

Philip A Jeffrey

Michael D Reed

Emil N Hahn

Roland Neumann

Grazyna E Muellner

Nandini Srinivasan

Dennis Cashen

Retiming means for retiming an incoming data stream,comprising clock generation means,for producing a plurality of clock signals,having the same frequency but differing phase, and signal processing means,for receiving both the plurality of clock signals,and the incoming data stream,and outputting a selected one of the clock signals,and a retimed data stream retimed in accordance with the selected clock signal. The signal processing means,includes comparison means for comparing the phase of the incoming data stream with the phase of the plurality of clock signals and selecting which clock signal to use on the basis of this comparison.

Retiming method and means

A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.

Method for synchronizing signals and structures therefor

A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written. Once the proper delay is determined by experimentation, the phase delay logic controls the phase of the transfer data control signal to request more data at the correct time, or present more data at the correct time, to allow maximum operating speed for the data converter.

Circuit and method of timing data transfers

A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.

Circuit and method of indicating data hold-time

A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

Serial data clock recovery circuit using dual oscillator circuit

A unique cellular telephone (100) digitally frequency locks to the received base station transmitter signal. The cellular telephone (100) includes a radio transceiver (106), a reference oscillator (104), and microcomputer (102) with memory therein for controlling the operation thereof. The radio transceiver (106) includes a phase-locked loop (PLL) synthesizer 120, a receiver mixer (122) followed by one or more gain stages (124), a phase detector (126), and a divider (128). The PLL synthesizer (120) generates a signal locked to the reference oscillator (104) that is mixed with the incoming base station transmitter signal in the receive mixer (122) to generate an intermediate frequency signal. The output of the reference oscillator (104) also feeds the divider (128), which divides the reference oscillator signal by an amount so as to generate the divided signal having a frequency substantially the same as the frequency of the intermediate frequency signal from the mixer (122). The output of the divider (128) and the amplified intermediate frequency signal from the amplifier (124) are both fed into the phase detector (126), which generates a binary error signal (110). The microcomputer (102) is responsive to the binary error signal (110) for frequency locking reference oscillator 104 to the received base station transmitter signal.

Digitally frequency-locking a radio transceiver to the received signal

A controller for a radiotelephone having the capability of operation in both a secure mode for call authorization and a nonsecure mode for user interface is disclosed. The nonsecure mode and secure mode of operation are both resident in a single microcontroller which runs the nonsecure operations until a requirement for the secure operation is requested during call placement. The nonsecure mode is disabled during the period of time the secure mode is operational and is reenabled upon completion of the secure mode operation. The secure mode cannot be accessed externally to the microcontroller.

Radiotelephone controller configured for coresident secure and nonsecure

A process to reduce the howl condition in a radiotelephone when the microphone picks up audio from the speaker. The condition is detected by first lowering the speaker volume (103) and measuring the microphone volume for a corresponding decrease (104). The speaker volume is then increased (105) and the microphone volume is again measured for a corresponding increase (106). If the microphone volume follows the speaker volume, a howl condition has been detected. To eliminate the condition without the volume fluctuations being noticed by the parties conversing, the microphone and speaker volume is reduced in small increments (114) until the condition is eliminated.

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Mesa, AZ, United States of America

David K Ford