Vlsi Technology, Inc.

Intel Corporation

Koninklijke Philips Corporation N.v.

Rf Micro Devices, Inc.

Philips Semiconductor, Inc.

Corrent Corporation

David K Cassetti

Lokpraveen B Mosur

Swaroop Adusumilli

James C Steele

Stephen T Palermo

Sailesh Bissessur

Philip Wszolek

Smita Kumar

Patrick Fleming

Rodney J Pesavento

Charles Arnold Lasswell

Naveen Lakkakula

Atul Kwatra

Brian N Fall

Christopher F Clark

Barry M Davis

Pradnyesh S Gudadhe

Brian Will

Nick Richardson

Nadim Khlat

Marcus Granger-Jones

Alexander Wayne Hietala

Nicholas Julian Richardson

Gary D Hicok

Sanjeev Jain

Franklyn H Story

Gary A Walker

Lee Noehring

Satish N Anand

Chad W Mercer

Koichi Eugene Nomura

Michael Privett

Christopher P Clark

Christopher Cunningham

Timothy L Wilson

Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

Compression engine with configurable search depths and window sizes

A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.

Selection of data compression technique based on input characteristics

In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.

Compression scheme with control of search agent activity

Example data compressors disclosed herein include a hash unit to identify a hash table entry matching a hash index determined for a current position of a data stream undergoing data compression, the hash table entry identifying one or more prior positions of the data stream. Disclosed example data compressors also include a match engine to perform data matching based on the current position of the data stream and the one or more prior positions of the data stream to determine a primary match result and a backward match result for the current position of the data stream. Disclosed example data compressors further include a results evaluator to determine an output match result for the current position of the data stream based on the primary match result for the current position of the data stream and a backward match result determined for a subsequent position of the data stream.

Hash-based data matching enhanced with backward matching for data compression

A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Multi-threaded queuing system for pattern matching

The present disclosure relates to RF circuitry having delay locked loop (DLL) circuitry that may be used to measure amplitude modulation-to-phase modulation (AMPM) distortion of an RF power amplifier during factory calibration or during real time operation of the RF circuitry. During a calibration mode, the DLL circuitry may be calibrated using a reference clock signal. During a phase measurement mode, the DLL circuitry may use the reference clock signal, which is representative of an RF input signal to the RF power amplifier, and a feedback signal, which is representative of an RF output signal from the RF power amplifier, to measure a phase difference between the RF input signal and the RF output signal. By measuring the phase difference at different amplitudes of the RF output signal, the AMPM distortion of the RF power amplifier may be determined and used to correct for the AMPM distortion.

Measuring phase shift in a radio frequency power amplifier

Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Apparatuses and methods for deterministic pattern matching

A packet processing system is embodied on an ASIC is optimized for processing IPSec security protocol packets in a hardware configuration. Embedded RISC processors operate with hardware support modules providing for IPSec packet processing at OC24 data rates and greater. IPSec packets are received through a streaming interface and buffered in an external memory. When the entire packet is in external memory, portions are buffered in a local memory for crypto-processing. As portions of the packets complete processing, the portions are buffered to an output portion of the external memory associated with the channel. When an entire packet competes processing, portions are buffered to a local memory for streaming. The hardware accordingly reduces the involvement of the RISC processors and significantly increases channel throughput providing for high-speed IPSec packet processing.

Method and system for high-speed processing IPSec security protocol packets

An arrangement controls an IC designed with multiple &ldquo;core&rdquo; circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

Method and arrangement for controlling multiple test access port control modules

An arrangement controls an IC designed with multiple &ldquo;core&rdquo; circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers. A TAP link arrangement, including a TAP link module and control signals coupled to each of the multiple TAP controllers, selectively multiplexes the input signals to the multiple TAP controllers and multiplexes the status and test signals provided by the multiple TAP controllers to an output port of the IC.

Method and arrangement for controlling multiply-activated test access port control modules

An arrangement controls an IC designed with multiple &ldquo;TLM'ed core&rdquo; circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple &ldquo;TLM'ed core&rdquo; circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

Method and arrangement for hierarchical control of multiple test access port control modules

A computer system includes a central processing unit (CPU), system read-only memory (ROM), a random access memory (RAM) and a system controller. The system ROM includes a reset vector. A portion of the RAM is used to shadow the system ROM. The system controller is connected between the CPU, the system ROM and the RAM. The system memory includes an internal memory for storing first data. The system memory also includes logic which, in response to receiving an access to a reset vector stored in the system ROM, returns the first data stored in the internal memory.

Efficient soft reset in a personal computer

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Method and apparatus for direct access to main memory by an I/O bus

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

Growing community of inventors

Tempe, AZ, United States of America

David K Cassetti