Microsemi Solutions (US), Inc.

Pmc-Sierra US, Inc.

Microchip Technology Inc.

Microsemi Storage Solutions (u.s.), Inc.

David Joseph Clinton

Janardan Prasad

Cheng Yi

Praveen Alexander

Larrie Simon Carr

Amrendra Kumar

Babysaroja Annem

Anil B Dongare

Lijish Remani Bal

Tao Zhong

Gary Nichols

Patrick Bailey

Manthiramoorthy Ponmanikandan

One or more examples relate, generally, to systems, methods and devices for performing authenticated encryption that provides assurance of the authenticity of data through the encryption and decryption processes.

Increased data integrity for authenticated encryption algorithms

A power-saving method and circuit in a data processing device comprising a data buffer. Data transfer commands associated with a data source and a data destination are received at the data processing device. The data transfer commands are accumulated until an amount of data associated with the read commands is greater than a predefined threshold. When the amount of data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a power saving mode. When the amount of data is at least the predefined threshold, the data buffer is signaled to exit the power saving mode following a predetermined delay. Processing of the commands and data in respective pipelines is monitored to time exiting of the buffer from the power saving mode for arrival of the data. Power saving mode use and thus power saving are optimized.

Power saving in multi-directional data transfer

The present disclosure provides a method of scheduling data processing at a pipelined data processing engine, and a command scheduler for scheduling data processing at the pipelined data processing engine. The command scheduler determines whether a first data stream is locked to the pipelined data processing engine based on a status of a current data frame of the first data stream in the pipelined data processing engine. The command scheduler will schedule a next data frame of the first data stream to the data processing engine if the first data stream is not locked to the pipelined data processing engine, or it will postpone the scheduling of the next data frame of the first data stream if the first data stream is locked to the pipelined data processing engine.

Method and apparatus for scheduling processing tasks in a pipelined engine

A method and apparatus for handling SGLs for out of order systems is disclosed. The method involves generating multiple Child IOs from an original IO, each Child IO being at the granularity of a storage side memory; generating separate SG lists for each Child IO; and processing each Child IO independently of other Child IOs and in order with each Child IO for data transfer. As each Child IO is generated at the granularity of the storage side memory, the Child IOs can be processed independently of each other and in-order within each Child IO. Thus, an out-of order IO transfer is transformed into an in-order IO transfer.

Apparatus and method for scatter gather list handling for an out of order system

A data integrity (DI) protection circuit and method provide overlapping DI protection without increasing memory requirements. Write data parity is checked after write data error correcting code (ECC) check bits are generated, which is stored with the write data in memory without storing the write data parity. A corrupt location cache stores the write address and a write response error is generated when a write data parity error or write address parity error is detected. Read data and read data ECC check bits retrieved from the memory are checked and single bit errors are corrected, while double-bit errors result in a read error response. Read data parity is generated, and the corrected read data and corrected read data ECC check bits are then checked for bit errors. The corrupt location cache is searched for the read address, and a cache hit results in a read error response.

Overlapping data integrity for semiconductor devices

A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.

System and method for scatter gather cache processing

A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Growing community of inventors

Coopersburg, PA, United States of America

David Joseph Clinton