Applied Materials, Inc.

International Business Machines Corporation

David Jon Lee

Qintao Zhang

Samphy Hong

Christian Jacobi

Anthony Saporito

Christian Zoellin

Jane Helen Bartik

Wei Zou

Jang-Soo Lee

Lei Zhong

Felix Levitov

Jason Appell

Peter Grimm Sutton

Eberhard Engler

David P Surdock

Wayne R Swart

Carlos Caballero

Vittoriano Ruscio

Aldrin Bernard Vincent Eddy

Jeffrey P Koch

Avishay Vaxman

Daniel G Deyo

Thomas Rozmus

Durgaprasad Chaturvedula

A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.

Endpoint optimization for semiconductor processes

Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Backside wafer dopant activation

Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

Self-aligned trench MOSFET

Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

Ion implantation to form trench-bottom oxide of MOSFET

A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.

Method for increasing photoresist etch selectivity to enable high energy hot implant in SiC devices

Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

Split-gate MOSFET with gate shield

A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.

Methods for forming planar metal-oxide-semiconductor field-effect transistors

According to one or more embodiments of the present invention, a computer-implemented method includes detecting an abnormal event in operation of a first partition from a plurality of partitions of a computer server, the first partition being associated with a set of processors of the computer server and with a set of computing resources of the computer server. The method further includes in response, determining the set of processors associated with the first partition. The method further includes adjusting one or more settings of the set of processors to increase the set of computing resources associated with the first partition to complete the abnormal event.

Increasing processing capacity of processor cores during initial program load processing

Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

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Poughkeepsie, NY, United States of America

David Jon Lee