Midmark Corporation

Dsm IP Assets B.v.

Other

Wave Computing, Inc.

Mips Holding, Inc.

Verizon Services Corporation

Lodgenet Interactive Corporation

David John Simpson

Rainer Bernhard Teufel

Jeffrey T DeBord

Jay F Perkins

Darin Gregory Whittington

Daniel A Albers

Connor James Osowski

Todd Linthicum

Michael C Couch

Ross E Zirkle

Kirk Emil Apt

Calin Constantin Solomon

James Casey Lippmeier

James P Wynn

Jun Wang

Leslie Richter

Nicholas Leonard Blackburn

Stephen Curtis Johnson

Jon Robert Neil Hamilton

Richard D Trauben

Linda Kennyhertz

Brian G Barnett

James E Curry

Alexander I McAllister

Terry G Jones

Malik Basri

Jackson Jones

John W Norris, Iii

Richard Douglas Trauben

Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A plurality of dimensions from a tensor is flattened into a single dimension. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. A direct memory access (DMA) engine coupled to the one or more processor clusters is configured. Addresses are generated based on the unique address space descriptors and the common address space descriptor. The plurality of dimensions can be summed to generate a single address. Memory is accessed using two or more of the addresses that were generated. The addresses are used to enable DMA access.

Processor cluster address generation

Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.

Integer matrix multiplication engine using pipelining

The present invention is directed to isolated nucleic acid molecules and polypeptides of thraustochytrid polyunsaturated fatty acid (PUFA) synthases involved in the production of PUFAs, including PUFAs enriched in docosahexaenoic acid (DHA), eicosapentaenoic acid (EPA), or a combination thereof. The present invention is directed to vectors and host cells comprising the nucleic acid molecules, polypeptides encoded by the nucleic acid molecules, compositions comprising the nucleic acid molecules or polypeptides, and methods of making and uses thereof.

Polyunsaturated fatty acid synthase nucleic acid molecules and polypeptides, compositions, and methods of making and uses thereof

An inductive power system including an inductive power transmitter coupled to a non-conductive medium, and a power cord that electrically couples the transmitter to an AC power source. The inductive power transmitter is configured to emit an electromagnetic field based on the received AC power. There is an inductive power receiver coupled to the non-conductive medium and separated from the transmitter, wherein the receiver is configured to receive the electromagnetic field after it has passed through the non-conductive medium and in response develop power. A power cord electrically couples the developed power to a power sink.

Induction driven lighting

A mobile workstation with adjustable height of the present disclosure may comprise a top assembly, an adjustment assembly, and a bottom assembly. Adjustment assembly may comprise telescopically engaged segments. One or more pulleys or pulley assemblies may be disposed within one or more of the segments to allow for withdrawing and retracting segments from one another at the same rate. Actuation of the raising or lowering of the overall height of the mobile workstation may be realized through either a manual actuation or an electronic element such as a linear actuator.

Mobile workstation with adjustable height

Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters. The executing is controlled by interrupts only when an uncertainty exists within the data flow graph.

Processor graph execution using interrupt conservation

Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m&#xd7;k and a second integer matrix with dimensions k&#xd7;n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j&#xd7;j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j&#xd7;j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.

Techniques for data manipulation using a matrix multiplication engine using pipelining are disclosed. A first and a second matrix are obtained for matrix multiplication. A first matrix multiply-accumulate (MAC) unit is configured, where a first matrix element and a second matrix element are presented to the MAC unit on a first cycle. A second MAC unit is configured in pipelined fashion, where the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and where a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle. Additional MAC units are further configured within the processor in pipelined fashion. Multiply-accumulate operations are executed in pipelined fashion on each of n MAC units over additional k sets of m cycles.

Matrix multiplication engine using pipelining

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San Jose, CA, United States of America

David John Simpson