Integrated Device Technology, Inc.

Cochlear Limited

David John Reid

Timothy Gillespie

John Chambers

Padraig Joseph Hurley

Mathew Ross Markey

Aspects of the present invention are generally directed to taking measurements in a hearing prosthesis. In an embodiment, a power circuit, which may be a switched mode power circuit, is shut down during performance of the measurements to reduce interference. Then, power capacitively stored by the power circuit is used to power the hearing prosthesis during performance of the measurements. In an embodiment, the power circuit increases its voltage just prior to performance of the measurements. This serves to increase the amount of energy capacitively stored by the power circuit and thus extends the period of time during which the measurements may be taken while the power circuit is shut off.

Sensitive measurements in a hearing prosthesis

An over-voltage tolerant input stage in a semiconductor device is disclosed. The input stage includes: an input pad for receiving an input signal to the semiconductor device, a buffer coupled to the input pad for buffering the input signal, a pullup circuit for limiting current in the input signal, a switching circuit coupled to the input pad for controlling the pullup circuit, and a voltage supply coupled to the input pad, the pullup circuit and the switching circuit. In operation, the switching circuit is enabled to cause the pullup circuit to stop current flow between the input signal and voltage supply in the event of an over-voltage condition.

Over-voltage tolerant multifunction input stage

Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ripple counter circuit has been reached. Related methods are also disclosed.

Ripple counter circuits in integrated circuit devices having fast terminal count capability and methods of operating the same

Integrated circuit charge pumps reduce parasitic charge injection from signals that drive control inputs of the charge pumps. This reduction in parasitic charge injection can be utilized to lower phase error when the charge pumps are used in phase-locked loops (PLLs). A charge pump may include an output current source and a control circuit that drives the output current source with control signals in a preferred manner. The output current source may include a totem pole driver therein. This totem pole driver includes at least an upper PMOS supply transistor and a lower PMOS current source transistor that are disposed in series in a pull-up path extending between an output of the driver and a power supply line (e.g., Vdd). The control circuit may include a pull-up control circuit that is configured to drive a gate of the upper PMOS supply transistor with a PMOS turn-on voltage in response to a leading edge of a pull-up control signal.

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Forestville, Australia

David John Reid