Plessey Semiconductors Limited

Gec-Marconi Limited

Mitel Semiconductor Limited

David John Pedder

Roger William Whatmore

David J Warner

Kim L Pickering

To provide trimmable inductor structure for a multichip module, direct-chip-attach or surface mount assembly in which an inductive element is formed on or near a surface of the assembly, a planar chip of dielectric or ferrite material is mounted over the inductive element, this chip having on its upper surface a trimmable metallization layer, which may for example be patterned in concentric rings or in a spiral.

Trimmable inductor structure

A testing apparatus for testing integrated circuits at the bare die stage includes a testing station at which microbumps of conductive material are located on interconnection trace terminations of a multilayer interconnection structure, these terminations being distributed in a pattern corresponding to the pattern of contact pads on the die to be tested. To facilitate testing of the die before separation from a wafer using the microbumps, the other connections provided to and from the interconnection structure have a low profile.

Bare die testing

Low profile microchip module assemblies are formed by first mounting one or more active semiconductor integrated circuit chips on a multilayer metallization and dielectric structure on a substrate of, say, silicon or alumina, by wire bonding or flip-chip solder bonding, and then inverting the substrate and mounting it on a printed circuit board by means of solder bump connections. The solder bump connections are sufficiently high for the chips to be held clear of the printed circuit board.

Microchip module assemblies

A test probe structure for making connections to a bare integrated circuit device or a wafer to be tested comprises a multilayer printed circuit probe arm which carries at its tip an MCM-D type substrate having a row of microbumps on its underside to make the required connections. The probe arm is supported at a shallow angle to the surface of the device or wafer, and the MCM-D type substrate is formed with the necessary passive components to interface with the device under test. Four such probe arms may be provided, one on each side of the device under test.

Structure for testing bare integrated circuit devices

In a multichip module structure comprising a silicon, alumina or sapphire substrate carrying a plurality of layers of metallisation separated by polymer dielectric layers, with one or more inductors formed in the uppermost metallisation layer, a ferrite core for one of those inductors is located over the inductor and secured in position by flip chip solder bonding.

Multi-chip module inductor structure

A ball grid array arrangement comprises a dielectric multilayer substrate, in a lower metallization layer of which is disposed an array of solder balls. A passive circuit element is integrated into at least one of the metallization layers. The arrangement may be either a discrete component consisting of a triplate transmission-line resonator or interdigitated filter integrated into an inner metallization layer and defined by that layer in conjunction with adjacent layers, or it may take the form of an IC carrier or multichip-module carrier having such transmission structures situated within a central die-attach area of the substrate and having also a peripheral area containing bonding structures for the mounting of at least one chip or chip module. There will normally be at least two groups of such bonding structures, and a passive circuit element in the form of an inductor may be formed in the upper metallization layer between adjacent groups of bonding structures.

Ball grid array arrangement

In a multilayer metallisation/dielectric structure on a silicon substrate a trimmable capacitor is formed between two of the higher metallisation layers, with one layer being segmented and the individual segments connected by way of one or more vias and respective narrow links to one terminal of the capacitor. The narrow links are formed from titanium tungsten on the oxide isolated silicon substrate.

Trimmable capacitor

A bare die testing apparatus comprising a multilayer interconnection structure 10 having a testing station 11 for testing the bare die 20, testing circuits and components 12 arranged in said structure adjacent the testing station 11, said testing station 11 having a plurality of microbumps 17 of conductive material soldered onto wettable metallization pads 18 located on interconnection trace terminations of the interconnection structure, said terminations being connected through the interconnections of the multilayer structure to said testing circuits and components 12. The microbumps 17 are distributed in a pattern corresponding to the pattern of contact pads 19 on a bare die 20 to be tested. A method of testing bare dies by the bare-die testing apparatus embodying the invention, the method including optically aligning the contact pads 19 of a bare die 20 under test with the microbumps 17 of the testing station 11, contacting the aligned contact pads 19 of the bare die 20 with the corresponding microbumps 17 of the testing station 11 and applying appropriate pressure on to bare die 20 to ensure desired low contact resitstance between the microbumps 17 and the contact pads 14.

Apparatus and method for testing bare dies with low contact resistance

A hybrid structure comprising a lens 10, an antenna array 8 and a semiconductor microcircuit 2. The antenna array 8 is formed on a surface of the lens 10 or on a surface of a substrate 14 having substantially the same refractive index as the material of the lens 10. Metal bump bonds 6, 12 provide connections between the antenna array 8 and the semiconductor microcircuit 2.

Hybrid structures

A flip-chip solder bonding arrangement including a semiconductor substrate having thereon layers of metallization which have a tendency to interact with a solder material, forming on said layers of metallization a barrier metallization layer which is not reactive with said solder material, forming solder pads on the barrier layer and thereafter forming solder bonds with such solder pads employing said solder material.

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Warwickshire, United Kingdom

David John Pedder