Arm Limited

David John Gwilt

Richard Roy Grisenthwaite

Bruce James Mathewson

Peter Guy Middleton

David Michael Bull

Andrew Christopher Rose

Antony John Harris

Ian Victor Devereux

Graeme Leslie Ingram

Christopher Edwin Wrigley

A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states. For a new multi-cycle arbitration operation to be performed by the arbitration circuitry, the filter circuitry selects one of the filter states that has not been selected for any other multi-cycle arbitration operation already in progress within the pipeline states of the arbitration circuitry. Then, it determines as candidate access requests for the new multi-cycle arbitration operation those access requests that are seeking to access a resource associated with the selected filter state. Such an approach allows efficient multi-cycle arbitration to take place even where the resources may have inter-access timing parameters associated therewith which prevent them from being able to receive access requests every clock cycle.

Data processing apparatus and method for performing multi-cycle arbitration

A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of said plurality of control channels, said buffer comprising: a data input port operable to receive said data being transferred using said plurality of control channels; a data output port operable to output data to be transferred using said plurality of control channels; and a data store operable to store data received from said data input port prior to it being output by said data output port, said data store comprising a plurality of storage locations each operable to store a data item, said storage locations being arranged in groups, a storage location being allocated to a group in dependence on the control channel that a data item that it stores is received from, such that each group comprises storage locations storing data items received from a same one of said plurality of control channels. Free storage locations are not allocated to any of the plurality of groups, so that new data items received can be stored in any of the free storage locations, these locations then being allocated to the group corresponding to the channel being used.

Buffering data during data transfer through a plurality of channels

A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffersare provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffersare responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

Bus transaction management within data processing systems

A data processing apparatus comprises a master device, a slave deviceand a communication busvia which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.

Transaction request servicing mechanism

The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access request of a second type should be performed without any intervening accesses taking place. The data processing apparatus has a processor operable to execute instructions, and a first master logic unit and a second master logic unit operable to process access requests generated during execution of those instructions. The access requests specify accesses to a slave device, with the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus. Routing logic is provided to determine, for each access request, which master logic unit is to process that access request, the first master logic unit being arranged to process access requests of the first type, and the second master logic unit being arranged to process access requests of the second type. The routing logic is arranged in the event of execution of the multi-access instruction to cause both the access request of the first type and the access request of the second type specified by the multi-access instruction to be processed by the first master logic unit. Further, the first master logic unit is arranged, when processing the access requests of the multi-access instruction, to issue a lock signal which is used to ensure that the first master logic unit is granted sole access to the slave device whilst the first master logic unit is processing the access requests of the first and second type. This approach enables the benefits of providing a separate master logic unit for accesses of the first type and a separate master logic unit for accesses of the second type to be realised, whilst enabling the above-described multi-access instruction to be executed in the desired manner, i.e. by ensuring that the access requests of the first and second type specified by the multi-access instruction are performed without any intervening accesses taking place.

Handling of a multi-access instruction in a data processing apparatus

A cache controller operable to control a cache comprising cache lines, each being operable to store data words and validity information indicating that all data words within that cache line are valid. The cache controller comprises a linefill mechanism operable to write data words to a cache line, to provide an indication when each of the data words has been written to the cache and to set the validity information when all data words in the cache line have been written; and a data word accessing mechanism, responsive to a request to access a data word during a linefill operation prior to the validity information being set, to determine from the indication provided by the linefill mechanism whether the data word to be accessed has already been written during the linefill operation and, if so, to provide a signal indicating that the data word is accessible.

Cache controller

A data processing system is provided having a main processor and a coprocessor . When in a debug mode, the main processor and the coprocessor are supplied with different instructions. The coprocessor is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor is supplied with a main processor data capture instruction (LDR). The coprocessor responds to the MCR instruction by controlling debug data representing state of the data processing apparatus to be placed upon a data bus from where it is read by the main processor under control of the LDR instruction.

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Cambridge, United Kingdom

David John Gwilt