International Business Machines Corporation

David John Geiger

Ruchir Puri

Paul Gerard Villarrubia

Haoxing Ren

Mihir Choudhury

Hung Cai Ngo

Bruce Martin Fleischer

Gi-Joon Nam

Shyam Ramji

Alexander Joel Suess

Myung-Chul Kim

Eli Arbel

Benjamin Neil Trombley

Andrew James Sullivan

Victor N Kravets

John Thomas Badar

Smita Krishnaswamy

Km Mozammel Hossain

Josiah Hamilton

A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

Hierarchy-driven logical and physical synthesis co-optimization

Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

Automated region based optimization of chip manufacture

Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.

Transformation on input operands to reduce hardware overhead for implementing addition

A method, system and computer program product for forming a netlist for an electronic circuit is disclosed. A Very High Speed Integrated Circuit Hardware Description Language (VHDL) file is created for a plurality of voltage domains. The VHDL file includes a voltage domain attribute and a logic voltage attribute for a pin of the electronic circuit. The voltage domain attribute and the logic voltage attribute for the pin are read from the VHDL file. Netlist instructions for the pin are synthesized to form a netlist for the electronic circuit. Synthesizing the netlist instructions begins with synthesizing netlist instructions within a voltage domain indicated by the voltage domain attribute and ends with synthesizing netlist instructions within a voltage domain indicated by the logic voltage attribute.

Multi power synthesis in digital circuit design

A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a 'placement force' that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a 'flattened' model of the design while respecting the movement boundaries. Following this &#x201c;flattened&#x201d; optimization, the placed &#x201c;unit-level&#x201d; cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.

Automated critical area allocation in a physical synthesized hierarchical design

Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.

Logic modification synthesis

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Poughkeepsie, NY, United States of America

David John Geiger