International Business Machines Corporation

David John Erb

Maximino Aguilar, Jr

Sidney James Manning

James Michael Stafford

Michael A Paolini

Michael Stan Gowen

Xiaoshan Z Odom

A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.

Adjusting CPU time allocated to next thread based on gathered data in heterogeneous processor system having plurality of different instruction set architectures

A method for visually displaying an indicator for preceding and succeeding source code lines being executed within a graphical debugging environment. The method includes displaying within a GUI source code lines for a segment of currently examined source code, displaying a visual indicator that is associated with a presently examined source code line, and determining a previously examined source code line, wherein the location of the previously examined line of source code is determined by the use of information that is associated with the previously examined line of source code. The method further includes displaying a visual indicator that is associated with the previously examined line of source code, determining a next source code line that is to be examined, and displaying a visual indicator that is associated with the next source code line that is to be examined.

Method for visually indicating preceding and succeeding source code lines that are executed in a graphical debugging environment

An approach of analyzing software performance without requiring hardware is presented. A timing description generator logs instruction performance characteristics for each of the assembly code's instructions. The performance characteristics identify whether an instruction issued or stalled during particular instruction cycles. Once the timing description generator cycles through the instructions and logs performance characteristics for each instruction, the timing description generator generates a performance graph. For each page line, the performance graph includes 1) dual-issue information if applicable, 2) instruction cycle counter values/stalled instruction identifier's that are positioned at corresponding line location values, and 3) the instruction. A developer may analyze the performance graph and identify code locations that require optimization in order to increase performance.

Analyzing software performance without requiring hardware

A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a 'no operation' (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other instructions are scheduled for the other. In this embodiment, the BISLED also serves the purpose of re-aligning the instruction stream so that instructions are placed in the correct pipeline based upon the function performed by the instruction.

System and method for simulating hardware interrupts

A method and apparatus is provided for analyzing performance of a computer or data processing system, during the time that a specified task is running on the system. The analysis is used to furnish a system user with a list of proposed hardware component upgrades that would improve system performance in various respects, each being accompanied by a parameter value indicating the improvement a particular upgrade would provide. Usefully, listed upgrades are made available over the Internet, for purchase by system users. In an embodiment directed to a method, for use with a computer system comprising a configuration of hardware components, selected hardware components are monitored as the system performs a specified task. This is done to acquire statistics representing the operation of respective selected components. The statistics are processed, to identify at least one selected component that impedes the system in performing the task. An upgrade of the identified component is then proposed, together with an indication of the improvement that would result if the upgrade is made.

Method and apparatus for analyzing computer system performance and proposing hardware component upgrades

Overall graphics performance in a computer graphics system is improved by an accelerated interface between high performance microprocessors and hardware adapters which is a combination of hardware and software and which is independent of specific computer languages. The interface was specifically designed for any hardware attached to a central processing unit (CPU) that does not enforce the order of memory accesses. The hardware supported process fools the CPU into thinking that the write and read are accessing the same address, thus guaranteeing that the order of the write and read are correct. In a first method, a hardware pseudo-address are created on the display adapter. When the software writes to the pseudo-address, the display adapter writes the data to the coordinate register. When the software reads from the pseudo-address, the display adapter returns the contents of the actual status address. In the second method, the software writes and reads from the coordinate address; however, when the software reads from the coordinate address, the display adapter does not return the contents of the coordinate address. Instead, the adapter actually reads and returns the contents of the status address.

Accelerated interface between processors and hardware adapters

A method is provided for distinguishing nonconvex polygons from complex polygons. The present invention compares the edges of a polygon for self intersection points. Initially, 'base' and 'compare' edges are designated and bounding boxes for each of these edges are determined. The bounding boxes are then compared and if they intersect the edges may have points in common, whereas if no intersection occurs, then there are no common points and the edges are incremented and a comparison of other edges occurs. If it is determined that bounding boxes intersect, the intersection point for the edges under consideration is determined. If this intersection point lies within both bounding boxes, then the polygon is complex and the test ends. However, if the intersection point is outside either bounding box, then the edges are incremented and processing continues until all relevant edges have been considered.

Growing community of inventors

Austin, TX, United States of America

David John Erb