International Business Machines Corporation

David John Craft

Charles Ray Johns

Harm Peter Hofstee

James Allan Kahle

Pradeep Kumar Dubey

Robert K Montoye

Michael Norman Day

Scott Whitney Gould

Frank Ray Keyser, Iii

John Samuel Liberty

Richard Greenberg

Brian A Worth

Daniel Jonathan Auerbach

Wendel Glenn Voigt

The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.

Security architecture for system on chip

A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.

Method and system for controlled distribution of application code and content data within a computer network

The present invention provides data encryption for a differential bus employing transitional coding. The present invention maps, encodes and encrypts input data as a logic status for a given bus transfer cycle. The mapping, encoding and encrypting of the input data changes from bus transfer cycle to bus transfer cycle. The mapping, encoding and encrypting is a function of a pseudo-random number. A logic status is differentially transmitted from a bus transmitter to a bus receiver, to be mapped, decrypted and decoded as the corresponding output data.

Dynamic system bus encryption using improved differential transitional encoding

The present invention provides for authentication of code, such as boot code. A memory addressing engine is employable to select a portion of a memory, as a function of a step value, as a first input hash value. The step value allows for the non-commutative cumulative hashing of a plurality of memory portions with a second input hash value, such as a previous hash value that has been rotated left. An authenticator circuit is employable to perform a hash upon the portion of memory and the second input hash value. A comparison circuit is then employable to compare an output of the authenticator circuit to an expected value.

Hardware-based secure code authentication

The present invention provides for validating downloaded code. Code is transferred to a volatile memory of a system on a chip from a source. The volatile memory is decoupled from the source of the transferred code through employment of an isolation bus. An embedded security value, associated with the downloaded code, is determined. The security value is compared to an unlock sequence stored within the non-volatile memory in the system on a chip. If the security value matches the unlock sequence, the downloaded code is allowed access to secure data stored in the non-volatile memory. If the security value does not match the unlock sequence, the downloaded code is denied access to the secure data stored in the non-volatile memory.

Method and system for ensuring security of code in a system on a chip

The present invention provides employing differential transitional encoding with a differential bus. Employing the differential transitional encoding comprises dividing the differential bus into one or more groups comprising four bus lines. Employment of the differential bus also comprises asserting half the bus lines of a group during a bus data transfer, thereby defining an asserted set of bus lines and a de-asserted set of bus lines. The method and system further comprises transmitting data by differentially driving two of the bus lines, one bus line per set, by de-asserting one of the bus lines of the asserted set, and asserting one of the bus lines of the de-asserted set.

Method and system for an improved differential form of transitional coding

An encoder for compressing data is described, including a history buffer having multiple storage locations for storing target data units. The encoder is configured to input a target data string including multiple target data units, and additional data (e.g., security data associated with the target data string). In the event the history buffer contains multiple matching strings that match the target data string, the encoder is configured to select a displacement value of one of the matching strings dependent on a portion of the additional data, and to produce a copy pointer corresponding to the target data string and including the selected displacement. The selected displacement value in the copy pointer conveys the portion of the additional data. A decoder for decompressing data is also described, including a history buffer having multiple storage locations for storing data units. The decoder is configured to input a copy pointer including a displacement value indicative of a location of a first data unit of a data string in the history buffer, to use the displacement value to determine the data string, and to use the displacement value to determine a value of a quantity of additional data conveyed by the displacement value in the event multiple copies of the data string exist in the history buffer. A system is described including the encoder and the decoder, as are methods for compressing and decompressing data.

System and methods for embedding additional data in compressed data streams

A method for adaptively compensating skews during data transmission on a bus is disclosed. A bus includes one or more groups of multiple signal paths. Each of the signal paths within a group is assigned a unique binary data value. During data transmissions, only one signal path within each group is activated at a time, and each activation of one of the signal paths represents its associated unique binary data value. Thus, a sequence of consecutive activations represents the same information as if the data were transmitted in parallel. Before signal transmission, a time delay between a transition on a first and a second of the signal lines is measured by utilizing a control frame. The time delay measurement is repeated to establish the relative time delays associated with all possible transitions on all the signal lines. In response to the measured time delays, an appropriate compensating delay is introduced accordingly before launching each transition on the signal lines. Such added delay compensates for the differences in delay (or skew) between the different transitions travelling along different signal paths.

Method and apparatus for adaptively compensating skews during data transmission on a bus

A method and apparatus for configuring redundant array of independent disks (RAID) are disclosed. A RAID includes a processor tray having a host processor, and a drive tray having a bridge chip and multiple attachment chips. The attachment chips are connected to each other in a loop configuration. Each of the attachment chips, which is assigned with an unique node ID, is connected to a respective disk drive. The host processor can direct more than one attachment chip to participate, in various ways, to a single data transfer around the loop. This is accomplished by directing the data transfer to a specified node ID, after configuring all the other attachment chips with temporary alias node ID identical to the specified node ID to which the data transfer operation is directed.

Method and apparatus for configuring redundant array of independent disks (RAID)

A method for transmitting data on a bus having multiple data lines is disclosed. Each of the data lines within the bus is assigned a unique binary value. During data transmissions, only one of the data lines within the bus is activated at a time, and each activation of one of the data lines represents its associated unique binary value. Thus, an aggregate of consecutive activations represents the same information as if the data were transmitted in parallel.

Method and apparatus for transmitting data on a bus

A method for interconnecting components within a data processing system is disclosed. A number of components is connected to an uni-directional bus. The uni-directional bus is arranged in a loop configuration. Each component has at least one node identification. Communications among these components are provided in the form of messages via a respective node identification. Each message includes a node identification field and a content field.

Method for interconnecting components within a data processing system

A method for compressing data within a data processing system is disclosed. Each unit of data is at least two bytes. As each byte from a data stream is received, a determination is made as to whether or not an identical data byte occurs at a pre-selected interval within a group of bytes already received. In response to a determination that an identical data byte occurs at a pre-selected interval within a group of bytes already received, only a portion of a subsequent unit of data from the data stream is passed to an output.

Method and system for compressing unicode data within a data processing

A system and method for providing data compression with high integrity is disclosed. In one aspect, the system and method includes a first interface, a second interface, and a storage. In this aspect, the method and system include providing a first compressor/decompressor coupled to the first interface and the storage providing and a second compressor/decompressor coupled to the second interface and the storage. The first compressor/decompressor compresses data from the first interface, decompresses compressed data from the storage, and provides a first data stream. The second compressor/decompressor compresses data, decompresses compressed data, and provides a second data stream. Each compressor/decompressor can monitor the input and output of the other compressor/decompressor using a common shared interface to the storage. The first compressor/decompressor monitors the second data stream and compares the second data stream to the first data stream if the second compressor/decompressor is a master device, and vice versa. In another aspect, the system has a storage means and an interface. The method and system include providing a single compressor/decompressor and error comparing means coupled with the compressor/decompressor. The compressor/decompressor alternatively compresses a portion of data and decompresses a portion of compressed data. The error comparing means compare the portion of data to the portion of the compressed data.

Storage sub-system compression and dataflow chip offering excellent data

An apparatus for improving I/O pin interfaces for serial data communications is disclosed. In accordance with a preferred embodiment of the present invention, an improved serial interface is provided, which comprises an oscillator input, a signal input, a counter, a register, and a data output. The counter is utilized to count the number of cycles of the oscillator input for which the signal input is asserted. The register is utilized to receive a value from the counter when the signal input is next de-asserted. The data output is at a first logical state when the signal input is asserted for fewer oscillation cycles than the value stored in the register and the data output is at a second logical state otherwise, such that only one I/O pin is required for serial communications.

Growing community of inventors

Austin, TX, United States of America

David John Craft