Arm Limited

David John Butcher

Robert James Catherall

Jeremy Isle Johnson

Stephen John Hill

Rhys David Copeland

Richard Roy Grisenthwaite

Andrew Christopher Rose

Vladimir Vasekin

David James Williamson

Wilco Dijkstra

Hedley James Francis

Matthew Paul Elwood

Rodolph Gérard Jacques Ascanio Jean-Denis Perfetta

Martyn Maurice Capewell

Andrew James Booker

Riaan Swart

Peter James Horsman

Sidath A Senanayake

A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage.

Content usage monitor

A method of performing a processing task in a data processing apparatus is provided that reduces memory usage of the processing task. According to this method a Virtual Machine performs the steps of accessing platform-neutral program code in a function repository, executing the processing task on the Virtual Machine, and analysing at a current execution point, on a function-by-function basis, which functions in the function repository are inactive functions. The Virtual Machine performs software-based unloading from the function repository of at least a portion of platform-neutral program code corresponding to one or more inactive functions. A corresponding virtual machine and data processing apparatus are also provided.

Software-based unloading and reloading of an inactive function to reduce memory usage of a data processing task performed using a virtual machine

A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to execute a shader program to generate a color value for the pixel. The shader program has multiple execution paths via which the color value may be generated, and which execution path is taken is dependent on the input data. An image buffer having a plurality of storage locations is provided, with each storage location being used to store the color value generated by the shader circuitry for an associated pixel. In a trace mode of operation, execution of the shader program by the shader circuitry causes a trace vector to be generated containing a plurality of items of execution path information indicative of the execution path taken, the trace vector comprising a plurality of fields, each field being used to store one item of execution path information. The trace vector as output is constrained to be of the same size as the color value, and in the trace mode of operation the trace vector is stored in one of the storage locations of the image buffer in place of the color value generated by the shader program. This has been found to provide an efficient mechanism for obtaining execution path data useful when performing a variety of debugging activities in respect of a shader program.

Apparatus and method for tracing activities of a shader program executed on shader circuitry of a data processing apparatus

A debug interface is disclosed that is operable to receive diagnostic signals from a host debugger, amend the diagnostic signals and send the amended diagnostic signals to a virtual machine operable to process a plurality of applications in parallel. The debug interface comprises: at least one port corresponding to at least one of said plurality of applications; and diagnostic signal processing logic; wherein said at least one port is operable to receive a diagnostic signal from said host debugger, said diagnostic signal specifying a diagnostic operation to be performed on an application running on said virtual machine; and said diagnostic signal processing logic is operable to determine which of said plurality of applications said received diagnostic signal pertains to in dependence upon said at least one port said diagnostic signal was received at, and to amend said received diagnostic signal to identify said application prior to sending said amended diagnostic signal to said virtual machine.

Diagnosing faults within programs being executed by virtual machines

A data processing system is provided that includes an instruction decoderresponsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Compare and branch mechanism

A processoris provided with an instruction decoderwhich is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

Null exception handling

A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.

Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding

A processor incorporates a branch prediction mechanism which acts to predict branch outcomes for predicted type branch instructions. The processor also supports non-predicted type branch instructions which are ignored by the branch prediction mechanism and are not subject to prediction. The impact of mispredictions degrading overall performance of the prediction mechanism is reduced by employing non-prediction type branch program instructions to represent/control branch operations when it is known that misprediction is likely for those branch operations.

Branch prediction apparatus for repurposing a branch to instruction set as a non-predicted branch

A data processing systemis provided which includes an instruction decoderresponsive to a handler branch instruction HLB, HBLP which includes an index value field to calculate a handler pointer in dependence upon a handler base address HBA and the index value field and then to branch to that handler pointer position. A handler programat the branch target is then executed following which a return is made to an address following the handler branch instruction using a link address value stored when the handler branch instruction was executed.

Growing community of inventors

King's Lynn, United Kingdom

David John Butcher