Hewlett-packard Company

Hewlett-packard Development Company, L.P.

David Jerome Johnson

Gregg Bernard Lesartre

Robert F Krick

Stephen R Undy

Daniel J Dixon

Paul L Rogers

A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.

System of and method for flow control within a tag pipeline

Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of the out-of-order execution processor. The DPRESLOT monitors the transactions between a system interface, e.g., the system bus, and an address reorder buffer slot (ARBSLOT) and/or between the system interface and a cache coherency check slot (CCCSLOT). When a cache miss is detected, the DPRESLOT causes one or more cache lines in addition to the data line, which caused the current cache miss, to be pre-fetched from the memory hierarchy into the cache memory (DCACHE) in anticipation that the additional data would be required in the near future. When a cache write back is detected as a result of a cache coherency check, the DPRESLOT causes one or more cache lines, in addition to the data line currently being written back, to be pre-flushed out to the memory hierarchy from the respective cache memory (DCACHE) of the processor that owns the line, in anticipation that the additional data would be required by the requesting processor in the near future. A logic included in the DPRESLOT prevents a cache miss request for the additional data when another request has already been made for the data.

Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor

Speculative pre-flush of data in an out-of-order execution processor system

An associative cache memory for a computer with improved cache hit times. All possible data items are presented to bus driver circuits, thereby deferring data selection as long as possible. Driving and multiplexing are combined. The output of tag comparison directly selects at most one set of driver circuits. As a result, the only processing time in series with tag comparison is driver circuit selection. Since the data selection delay in series with tag comparison delay is reduced, the time delay is reduced for a clock edge for data driving after tag comparison, thereby enabling a faster clock.

Associative cache memory with improved hit time

A unified bi-directional LFSR is fabricated from latches having dual (Forward and Reverse) inputs. Each such latch accepts its inputs upon receipt of a clock signal that is respectively associated with the forward or reverse direction. The appropriate collection of XOR gates exists between latch outputs and the inputs associated with a forward clock signal, so as to produce the forward sequence. Likewise, another appropriate collection of XOR gates exists between the latch outputs and the inputs associated with the reverse clock signal. To produce a 'reverse' LFSR corresponding to the polynomial that is the reciprocal of the polynomial for the 'forward' LFSR, the latches of the reciprocal (reverse direction) LFSR are construed as being numbered in the opposite order. That is, a single set of latches (register) has both a forward linear feedback network and a reverse linear feedback network. Only one of these two feedback networks is used at a time, but they can intermix forward and reverse steps and appear to index back and forth along the native sequence of the LFSR. That is, steps in reverse undo the most recent forward steps, and vice versa. The bi-directional LFSR is also equipped with a way to preset the latches to a preselected initial value, and it is compatible with the production of all zeros. This last feature is obtained by including an extra latch in the register �(n+1)-many latches for a desired n-many bit word! and using it as a valid bit to qualify as correct the remaining latches in the register.

Growing community of inventors

Ft. Collins, CO, United States of America

David Jerome Johnson