Sun Microsystems, Inc.

Oracle International Corporation

David Jeffrey

Clement Fang

Neil Duncan

Gregory Frederick Grohoski

Heechoul Park

Tayung Wong

Lik Cheng

Nagaraj P Mitty

John Carrillo

Steven C Krow-Lucal

Jay C Robinson

Nikhil Vaidya

Dong Tran

Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Detection of multiple accesses to a row address of a dynamic memory within a refresh period

A memory module for use in a two rank memory module system includes a plurality of memory devices and a control circuit. In one embodiment, the control circuit may be configured to generate a chip select signal that is provided to each of the memory devices. The chip select signal may be dependent upon assertions of a first bank chip select signal and a second bank chip select signal received from a memory controller. The control circuit may be further configured to generate an address signal that is provided to each of the memory devices. The address signal may be asserted dependent upon which of the first bank chip select signal and the second bank chip select signal are asserted.

Single rank memory module for use in a two-rank memory module system

A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Memory expansion module with stacked memory packages and a serial storage unit

A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.

Memory module test system with reduced driver output impedance

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Santa Cruz, CA, United States of America

David Jeffrey