Honeywell International Inc.

David Jay Kessler

David Paul Campagna

David R Bueno

Brett Douglas Oliver

Eric Grobelny

Alvin Badillo

Barry Lawrence Allred

A system for interfacing Ethernet with SpaceWire comprises a processor including an Ethernet MAC, and a bridge device connected between the processor and a SpaceWire subsystem or network. The bridge device comprises a SpaceWire physical interface that receives SpaceWire data packets, and an Ethernet MAC packet builder that includes digital logic for segmentation of the data packets into Ethernet compatible packet segments. An Ethernet media independent interface receives the packet segments from the packet builder and outputs the packet segments to the Ethernet MAC. The Ethernet media independent interface also receives Ethernet data packets transmitted from the Ethernet MAC. An Ethernet MAC packet extractor receives the Ethernet data packets from the Ethernet media independent interface and includes digital logic for performing reassembly of the Ethernet data packets into SpaceWire compatible data packets, which are sent to the SpaceWire physical interface for transmission to the SpaceWire subsystem or network.

Ethernet to spacewire bridge

A processing unit comprises a plurality of individual integrated circuits (ICs) electrically connected to one another via a common configuration of electrical interconnects (e.g., through-silicon vias). At least two of the ICs may be configured for a different function. In some examples, the processing unit is formed by selecting the ICs from stored groups of ICs. The stored ICs can be, for example, modular ICs in that the ICs can be mixed and matched in any suitable number or type in order to meet a particular set of functional requirements for the processing unit, which may depend on the application for the processing unit. Electrical coupling of these individual ICs via the electrical interconnects of the ICs results in a single processing unit that is configured to perform functions specifically suited for a particular application or set of applications.

Processing unit comprising integrated circuits including a common configuration of electrical interconnects

A cache system to compare memory transactions while facilitating checkpointing and rollback is provided. The system includes at least one processor core including at least one cache operating in write-through mode, at least two checkpoint caches operating in write-back mode, a comparison/checkpoint logic, and a main memory. The at least two checkpoint caches are communicatively coupled to the at least one cache operating in write-through mode. The comparison/checkpoint logic is communicatively coupled to the at least two checkpoint caches. The comparison/checkpoint logic compares memory transactions stored in the at least two checkpoint caches responsive to an initiation of a checkpointing. The main memory is communicatively coupled to at least one of the at least two checkpoint caches.

Architecture and method for cache-based checkpointing and rollback

A method to enable an adaptive fault tolerance in a data system is provided. The method includes communicatively coupling a radiation hardened hardware element to at least one interrupt service routine application in a respective at least one processing element, triggering an interrupt service routine by an interrupt signal received from the radiation hardened hardware element at the interrupt service routine application after an execution of a code block by the at least one processing element, and inspecting the internal state of the at least one processing element to determine if an error occurred.

Growing community of inventors

Tampa, FL, United States of America

David Jay Kessler