International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

David James Stanek

Richard Leo Galbraith

Jonathan Darrel Coker

Evangelos Stavros Eleftheriou

Roy Daron Cideciyan

Thomas Mittelholzer

Ajay Dholakia

Weldon Mark Hanson

Travis Roger Oenning

David Robison Hall

Frank Ray Keyser, Iii

Walter Hirt

Peter John Windler

Rick Allen Philpott

Joe Martin Poss

Michael Joseph Ross

Allen Prescott Haar

Jeffrey L Furlong

Mark Andrew Bergquist

Gregory Scott Bush

Mark D Warne

A method of correcting repeatable run out (RRO) errors for a HDD in which RRO data is instead stored in consolidated form within the reserved area of the disk, instead of storing RRO data in the servo patterns for each HDD track or sector. RRO data is preferably stored in the reserved area of a hard disk drive in compressed form. The compressed RRO data is subsequently read into DRAM in compressed form and then decompressed for use. Predictive techniques determine what compressed RRO data is needed for upcoming read/write operations.

Method of compensating for repeatable runout error

An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.

Apparatus for providing dynamic equalizer optimization

A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

Method and apparatus for implementing soft-input/soft-output iterative detectors/decoders

Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state. The selector function utilizes the low latency detector output and selects the state of the path memory. The selector function provides a low latency output corresponding to the selected state. The low latency output is used for generating the timing error signal during a read operation.

Method and apparatus for enhanced timing loop for a PRML data channel

Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j&plus;1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k&plus;1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.

Data coding for data storage systems

An apparatus and method for transferring data between a read/write transducer coupled to a data channel and a data storage medium eliminates the necessity of a data sector block coding pad field. A data sector is received during a read operation. A disable signal associated with a last block of the data sector is generated. In response to the disable signal, data correction, such as parity correction, to the last block of the data sector is disabled. Data correction is enabled for application to blocks of the data sector other than the last block. Generating the disable signal involves identifying the last block of the data sector, which may be accomplished by detecting a change of state of a read gate input into the data channel or by use of a counter. The apparatus and method of the present invention may be embodied within a data channel of a data storing system, such as a direct access storage system.

Pad eliminating decoding method and apparatus for a direct access storage device

Methods and apparatus are provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using both partial matched filter and matched filter metrics. In the method of the invention, branch metric terms are transformed to shift all time varying terms and some constant terms after an add compare select (ACS) unit. The total number of non-zero constants on trellis branches is minimized. The shifted time varying terms and the shifted constant terms are added directly to state metric terms. The time varying terms are expressed as outputs Z of a partial matched filter or as outputs W of a matched filter. For a given generalized partial response target, the time-invariance property of the Viterbi detector enables identifying the minimum number of non-zero constants on trellis branches without resorting to heuristics. The time-invariance property holds for Viterbi detectors that process multiple samples per trellis-branch, thus allowing implementations at any desired speed.

Method and apparatus for viterbi detection of generalized partial response signals using partial matched filter and matched filter metrics

Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Z of a partial matched filter or as outputs W of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow. The two-way compare for comparing first and second state metric input values can include a hard shift for providing an add for the first state metric input value and then a compare between a resultant first state metric input value and the second state metric input value.

Method and apparatus for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed

A combined read and write VCO for data channels is disclosed. The combined read and write VCO for data channels shares a common loop capacitor while providing optimal read and write VCO loop responses, and allows the VCO to relock to the write timebase after a read very quickly while maintaining an accurate timebase. The combined read and write VCO includes an oscillator providing an output signal having a frequency that varies proportionately to an oscillator input signal and an adjustable voltage source, the adjustable voltage source having a first configuration for a write mode and a second configuration for a read mode, and the adjustable voltage source providing the oscillator input signal to the oscillator in response to receiving an input current signal. The adjustable voltage source includes a first and second capacitor coupled in series and a switch coupled across the second capacitor, the switch being open to provide the first configuration and closed to provide the second configuration. The oscillator further includes a transconductance amplifier for receiving the input signal from the adjustable voltage source and converting the input signal to a current signal having a first current value, a current modifier, the current modifier providing a current phase signal according to whether a write or a read mode is selected and whether an acquisition or track mode is selected, an adder, coupled to the transconductance amplifier and the current modifier, the adder modifying the current signal according to the current phase signal to produce an adjusted current signal and a current controlled oscillator, coupled to the adder, the current controlled oscillator receiving the adjusted current signal and producing an output signal having a frequency proportional to a magnitude of the current of the adjusted current signal.

Combined read and write VCO for DASD PRML channels

A noise-predictive data detection method and apparatus are provided for enhanced noise-predictive maximum-likelihood (NPML) data detection in a direct access storage device. A data signal from a data channel in the direct access storage device is applied to a maximum-likelihood detector that provides an estimated sequence signal. A noise bleacher filter having a frequency response of (1+.alpha.D)/1-.beta.D.sup.2) receives a combined estimated sequence signal and data signal and provides a noise filtered signal. A matching and error event filter receives the noise filtered signal and provides an error event filtered signal. An error correction unit receives the estimated sequence signal from the maximum-likelihood detector and receives the error event filtered signal and provides an error corrected estimated sequence signal.

Enhanced noise-predictive maximum likelihood (NPML) data detection

Methods and apparatus are provided for detecting servo information in a direct access storage device. A plurality of data symbols are read from a disk to produce a readback signal. Each data symbol and each sequence of data symbols contains servo identification information. A correlation filter provides a matched filter function of an expected readback signal of the plurality of data symbols to produce a correlated readback signal. A threshold detector is coupled to the correlation filter for identifying a threshold signal representative of the data symbol. A data separator responsive to the threshold detector windows the threshold signal and provides clock and data signals. The data separator includes a digital variable frequency oscillator (VFO) which optimally centers incoming servo information from the disk in a timing window and provides standard clocked data for a servo processor. The threshold detector has a variable threshold voltage that is programmed using a trim digital-to-analog converter (DAC).

Method and apparatus for servo data pattern detection

A method and apparatus are provided for gain adjustment of a signal. A plurality of comparators compare the signal with a plurality of threshold values. An envelope detector coupled to the comparator includes a peak capture function for detecting the amplitude of the signal and a polarity memory for detecting polarity of the signal. A gain control function for setting a gain correction value is responsive to the peak capture function and the polarity memory. Features of the signal gain adjustment method and apparatus of the invention include an intelligent hold of the gain control over both thermal asperities and null gaps in the signal.

Intelligent envelope detector and method for gain control for PRML data

Apparatus and method for providing equalization adjustment for a filter are provided in a PRML data channel. A first predetermined test pattern is written. Relative error is measured in both magnitude and phase for predetermined frequencies. A relative magnitude ratio for the predetermined frequencies and a phase delay between the predetermined frequencies are identified. A tap set is generated having predefined frequency responses at a plurality of predefined discrete frequencies.

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Rochester, MN, United States of America

David James Stanek