United States of America as Represented by the Administrator of Nasa

Ohio Aerospace Institute

David James Spry

Philip G Neudeck

Michael J Krasowski

Norman F Prokop

J Anthony Powell

Dorothy Lukco

Glenn M Beheim

Charles A Blaha

Carl W Chang

Jose M Gonzalez

Liangyu Chen

Kimala L Laster

Roger D Meredith

Andrew J Trunek

Kelley M Moses

Methods and devices are disclosed for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input. The second device is located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input.

Compensation for device property variation according to wafer location

An integrated circuit chip includes a wide bandgap semiconductor substrate, a plurality of semiconductor electronic components disposed on the semiconductor substrate, an overlying insulating layer disposed on the plurality of semiconductor devices, and a crack barrier laterally displaced from all of the plurality of semiconductor components. The crack barrier is configured to prevent propagation of cracks in the overlying insulating layer. The crack barrier does not conductively connect to any of the plurality of semiconductor electronic components.

Reliability extreme temperature integrated circuits and method for producing the same

A process of fabrication and the resulting microelectronic device that realizes metal features with larger lateral areas to maintain damage-free integrity over larger temperature ranges. The process and device enable the realization of highly durable extreme-environment microelectronic integrated circuits with increased functional capability, including realization of larger-area on-chip integrated metal-insulator-metal capacitor devices.

Larger-area integrated electrical metallization dielectric structures with stress-managed unit cells for more capable extreme environment semiconductor electronics

A durable bond pad structure is described that facilitates highly durable electrical connections to semiconductor microelectronics chips (e.g., silicon carbide (SiC) chips) to enable prolonged operation over very extreme temperature ranges.

Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Interconnection of semiconductor devices in extreme environment microelectronic integrated circuit chips

An iridium interfacial stack ('IrIS') and a method for producing the same are provided. The IrIS may include ordered layers of TaSi, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

Iridium interfacial stack (IRIS)

A method and the benefits resulting from the product thereof are disclosed for the growth of large, low-defect single-crystals of tetrahedrally-bonded crystal materials. The process utilizes a uniquely designed crystal shape whereby the direction of rapid growth is parallel to a preferred crystal direction. By establishing several regions of growth, a large single crystal that is largely defect-free can be grown at high growth rates. This process is particularly suitable for producing products for wide-bandgap semiconductors, such as SiC, GaN, AlN, and diamond. Large low-defect single crystals of these semiconductors enable greatly enhanced performance and reliability for applications involving high power, high voltage, and/or high temperature operating conditions.

Growing community of inventors

Medina, OH, United States of America

David James Spry