International Business Machines Corporation

Advanced Micro Devices Corporation

Altera Corporation

David James Shippy

James Allan Kahle

Christopher Michael Abernathy

Charles Ray Johns

Thuong Quang Truong

Jonathan James DeMent

Michael Norman Day

Ronald P Hall

Larry Edward Thatcher

Hung Qui Le

Harm Peter Hofstee

Albert James Van Norstrand, Jr

Kurt Alan Feiste

David Scott Ray

Robert Alan Philhower

Bruce Joseph Ronchetti

Donald J Hanrahan

Martin Langhammer

Gerald George Pechanek

Brian David Barrick

Peichun Peter Liu

Timothy Hume Heil

Dwain Alan Hicks

Takeki Osanai

Takeshi Yamazaki

Jeffrey Powers Bradford

Sandra S Woodward

Mark C Snedaker

Jeffrey Eastlack

Christopher Hans Olson

Brian Mitchell Bass

Kevin Franklin Reick

Robert Alan Cargnoni

Marlin Wayne Frederick, Jr

Jeffrey Douglas Brown

Charles Roberts Moore

Timothy A Elliott

Kimberly Marie Fernsler

Thomas L Jeremiah

Robert Greg McDonald

John Edward Derrick

Alfred T Rundle

Albert John Loper

Brice J Feal

Timothy V Bolan

David Benjamin Shuler

George A Fax

Josephine A Boston

Bruce J Morehead

Kimberly Marie Fensler

Bernhard Laubli

David A Ring

An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

Accelerator architecture on a programmable platform

A power throttling queue includes a queue and a throttling circuit. The queue has multiple entries. Each entry has a data field and a valid field. The multiple entries include a first portion and a selectively disabled second portion. The throttling circuit is coupled to the queue, and selectively disables the second portion in response to a number of valid entries of the first portion.

Power throttling queue

A data processor includes an execution unit having a multiple number of redundant resources, and a configuration circuit having first and second modes, wherein in the first mode, the configuration circuit enables the multiple number of redundant resources, and in the second mode, the configuration circuit disables the multiple number of redundant resources.

Dynamic re-configuration for low power in a data processor

A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.

Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates

Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.

Power throttling apparatus

A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.

Method and apparatus for delaying a load miss flush until issuing the dependent instruction

Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

Time-of-life counter for handling instruction flushes from a queue

Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache 'hits' and 'misses' and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a &#x201c;miss,&#x201d; the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.

Handling data cache misses out-of-order for asynchronous pipelines

A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.

Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor

The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Load address dependency mechanism system and method in a high frequency, low power processor system

Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

Dynamic power management in a processor design

An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only capable of utilizing a single register file. However, when register files of other thread are unused, the system resources are wasted. In the modified architected register file system, though, threads are enabled to utilize register files of other threads. The utilization of other thread registers is through the use of control fields added to a Status and Control Register (SCR) associated with each register file that enable and disable usage of other register files.

Architected register file system utilizes status and control registers to control read/write operations between threads

Power throttling method and apparatus

Time-of-life counter design for handling instruction flushes from a queue

Growing community of inventors

Austin, TX, United States of America

David James Shippy