Arm Limited

Advanced Risc Machines Limited

David James Seal

Richard Roy Grisenthwaite

Nigel John Stephens

David Vivian Jaggar

Dominic Hugo Symes

Christopher Neal Hinds

Simon Andrew Ford

Paul Kimelman

Vladimir Vasekin

Wilco Dijkstra

David Terrence Matheny

Edward Colles Nevill

Lee Douglas Smith

Simon John Craske

David Walter Flynn

David Hennah Mansell

Andrew Christopher Rose

Daniel Kershaw

Guy Larri

Philippe Jean-Pierre Raphalen

Christopher Bentley Dornan

Andrew Burdass

Jonathan Sean Callan

Michael Robert Nonweiler

Alexander Edward Nancekievill

Christopher Pedley

Richard York

David Aaron Rusling

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Data processing apparatus and method for processing a SIMD instruction specifying a control value having a first portion identifying a selected data size and a second portion identifying at least one control parameter having a number of bits that varies in dependence on a number of bits comprised by the first portion

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

Operand size control

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. Bitwise logical instructions are also described.

Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction

A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Address generation in a data processing apparatus

An instruction decoder () is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry () to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry () passes a test condition, then performing a compare operation on a first operand and a second operand and setting the current condition state to a result condition state generated during the compare operation; and (ii) if the current condition state fails the test condition, then setting the current condition state to a fail condition state specified by the conditional compare instruction. The conditional compare instruction can be used to represent chained sequences of comparison operations where each individual comparison operation may test a different kind of relation between a pair of operands.

Conditional compare instruction

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Apparatus and method for processing a bitfield manipulation instruction having a control value indicating insertion or extraction form

A processoris provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.

Mapping between registers used by multiple instruction sets

A data processing systemincludes a processor coreand a memory. The processor coreincludes processing circuitrycontrolled by control signals generated by decoder circuitrywhich decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.

Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands

Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.

Protected function calling

A processor coreis provided with an interrupt controllerwhich serves to set an interrupt mask bit F and a hardware control when an interrupt fiq occurs. A masking control signal NMI serves to either allow or prevent the software clearing of the interrupt mask bit F.

Interrupt masking control

A register data storeis provided within a data processing system. The register data storemay be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S, Sfor the multiple SIMD data elements to be manipulated by that data processing instruction. A given data processing element may be accessed via different registers depending upon the mapping between the register specifier, the register size and the data element size to a particular location within the register data store

Aliasing data processing registers

The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data processing apparatus of the present invention comprises a data processing unit for executing instructions which is responsive to the endian reverse instruction to apply an endian reverse operation to an input data word Rm comprising a plurality of data values. The endian reverse operation yields a result data word Rd given by: treating the input data word as consisting of a plurality of input sections, the result data word having a corresponding plurality of result sections, at least one input section comprising a plurality of data values; and for at least one of the input sections comprising a plurality of data values, performing an independent swap operation on the data values within that input section to form the result data word Rd in which the corresponding result section has its data values swapped with respect to that input section. This provides a particularly efficient technique for providing endian reversal functionality within a data processing apparatus supporting a variety of data structures, such as packed halfwords, zero extended halfwords, sign extended halfwords, etc.

Data processing apparatus and method for utilizing endianess independent data values

A data processorhas privilege levels associated with it including a user level and a privileged level. The processoralso has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack. If the system is not at the base level of activation, then the main stack is used to save state variables when an exception occurs rather than the process stack.

Stack memory selection upon exception in a data processing system

A data processing apparatusis provided which supports two instruction sets. These two instruction sets share a common subset of instructions including at least one class of instructions, such as all of the coprocessor instructions. The common subset of instructions have the same instruction encoding once any differences due to storage order within memory have been compensated for e.g. endianness.

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Cambridge, United Kingdom

David James Seal