Juniper Networks, Inc.

David James Ofelt

Jean-Marc Frailong

Pradeep S Sindhu

Srihari Raju Vegesna

Sarin Thomas

Chang-Hong Wu

Philip A Thomas

Jeffrey Glenn Libby

Dennis C Ferguson

Massimiliano Salsi

Murat Arabaci

Marianna Pepe

Kireeti Kompella

Deepak Goel

Debashis Basu

Anurag P Gupta

Chi-Chung Kenny Chen

Aibing Zhou

Vaishali Kulkarni

Wing Leong Poon

Steven Wilson Turner

Stephen Wilson Turner

David P Chengson

John Delmar Johnson

Abhijit Ghosh

Srinivas Perla

Oren Kerem

Bhavesh Patel

Edward C Priest

David Skinner

Xianzhi Li

Granthana Kattehalli Rangaswamy

Venkatraman Chandrasekaran

Jon G Losee

Hongsheng Ping

Karthikeyan Veerabadran

Ravi K Damaraju

A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

Methods and apparatus for clock gating processing modules based on hierarchy and workload

In some embodiments, an apparatus includes an optical transceiver which includes a rate-adaptive forward error correction (FEC) encoder and a rate-adaptive FEC decoder. The rate-adaptive FEC encoder is configured to adjust a number of a set of known symbols associated with a codeword to achieve rate adaption. A length of the codeword is fixed. The rate-adaptive FEC encoder is configured to generate the codeword based on (1) a set of information symbols including the set of known symbols and a set of data symbols, and (2) a fixed number of a set of parity symbols generated using information symbols. The rate-adaptive FEC decoder is configured to receive a set of reliability values associated with a channel word, and expand the set of reliability values to produce an expanded set of reliability values. The rate-adaptive FEC decoder is further configured to decode the expanded set of reliability values.

Methods and apparatus for flexible overhead forward error correction (FEC) sub-system for optical fiber communication systems

In an example of this disclosure, a method may include receiving, by a bit error location analyzer, a split information signal at a second data rate derived from an information signal at a first data rate. In this example, the second data rate is less than the first data rate, and the bit error location analyzer may be incapable of performing error analysis at the first data rate The method may include performing error analysis, by the bit error location analyzer, on information represented by the split information signal. In some examples, performing error analysis may include comparing the information represented by the split information signal to an information seed to determine a plurality of bit error locations in the information represented by the split information signal relative to the information seed.

Systems and methods for error detection and correction

Techniques are described for determining pre-compensation parameters to compensate for signal integrity degradation along a signal path. A processor generates a first digital signal and receives a second digital signal. The second digital signal is generated from an optical-to-electrical conversion of a feedback optical signal that is generated from an electrical-to-optical conversion of an electrical signal by an optical module. The processor determines the pre-compensation parameters based on the first and second digital signals.

Self-calibration of pluggable optical module

The invention is directed to techniques for supporting multi-link protocols within a computer network. In one embodiment, a method includes receiving a set of data blocks from a plurality of links in one or more interface cards according to a multi-link protocol and sending the data blocks to a multi-link service card for sequencing. The data blocks may then be sent to the one or more interface cards for communication to a destination device over a computer network. Implementing a multi-link service card may allow a network device, such as a router, to support multi-link protocols.

Multi-link routing

In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.

Deadlock-resistant fabric tree replication in a network device

In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.

Methods and apparatus for transmission of groups of cells via a switch fabric

In general, techniques of the present disclosure relate to synchronizing concurrent access to multiple portions of a data structure. In one example, a method includes, sequentially selecting a plurality of requests from a request queue, wherein at least one of the requests specifies a plurality of requested synchronization objects for corresponding candidate portions of a data structure to which to apply an operation associated with a data element. The method also includes querying one or more sets of identifiers to determine whether one or more of the requested synchronizations objects specified by the selected request are acquirable. The method also includes acquiring each of the requested synchronization objects that are acquirable. The method includes, responsive to acquiring all of the one or more requested synchronization objects, selecting a subset of the candidate portions of the data structure and applying the operation only to the selected subset of the candidate portions.

Acquisition of multiple synchronization objects within a computing device

In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.

Memory error protection using addressable dynamic ram data locations

In general, techniques are described for packet queuing within ring networks. In accordance with the techniques, a network device of a ring network comprises a memory having a different queue for each order-dependent pair of the network devices. Each pair represents a different order-dependent combination of the network devices that includes an ingress network device that provides an ingress to the ring network and an egress network device that provides an egress from the ring network. The network device further comprises an interface for receiving a packet from a neighboring one of the plurality of network devices and a control unit that, in response to receiving the packet, stores the packet to one of the queues based on which network devices is the ingress and which network device is the egress for the packet. The control unit forwards the stored packet via the ring network according to a scheduling algorithm.

Packet queueing within ring networks

A device for managing multiple instructions to access multiple wide registers may include logic to receive the multiple instructions to access one of the multiple wide registers, associate each received instruction with a corresponding one of multiple buffer memories, and allow simultaneous processing of the multiple instructions associated with each of the multiple buffer memories, where the multiple instructions are processed such that data is transferred between the multiple buffer memories and the multiple wide registers in one operation.

Systems and methods for accessing wide registers

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Los Gatos, CA, United States of America

David James Ofelt