National Semiconductor Corporation

David James Megaw

Paul David Ranucci

Gregory J Smith

Steve A Martinez

Glenn Chance Dunlap, Iii

A circuit for recovering charge at the gate of an output transistor arranged to drive the output of a switching circuit such as a switching regulator or controller. A substantial portion of the charge for each switching cycle is recovered under a wide range of load conditions for the switching circuit, e.g., no load, partial load, or full load. Also, charge recovery operates effectively with a switching circuit that is arranged to switch in a synchronous or asynchronous manner. Additionally, if the output voltage of a switching circuit is 12 or more volts, the amount of charge that can be saved can be relatively substantial.

Power FET gate charge recovery

A method and circuit for controlling the start-up of a shunt regulator that uses an error amplifier for normal operation in a linear range of a target value output voltage set by a reference voltage upon circuit start-up clamps the output voltage to a first level value below the target value, next applies regenerative positive feedback independent of the error amplifier to force the output voltage through a range where adverse conditions can occur to a second level value below the target value, and then releases the positive feedback near the target value where the error amplifier assumes control of the regulation.

Start-up circuit for a shunt regulator

A system and method is disclosed for providing communication of an over-current protection signal and current mode control signals between a controller chip and a power chip in an integrated circuit device that comprises a plurality of integrated circuit chips. The controller chip sends pulse width modulation signals and a reference current signal to the power chip. Current flow status detection circuitry in the power chip detects a current flow status in the power chip and provides a current flow status signal to the controller chip. The current flow status signal may comprise an over-current protection signal or current mode control signals. One advantageous embodiment of the invention comprises a switch mode power supply integrated circuit.

System and method for providing communication of over-current protection and current mode control between multiple chips in an integrated circuit

A circuit for providing a self-stabilizing, differential load circuit with well controlled complex impedance to an amplifier is described. According to an embodiment, two pairs of transistors in a cross-coupled configuration, a degeneration resistor for each transistor, and parasitic capacitance cancelation capacitors provide a self-stabilizing, differential load. Small signal analysis of the circuit illustrates an impedance of the load circuit to be substantially equal to a combination of impedance values with substantially little dependence on transconductances and incremental resistances of the transistors over an extended frequency range. By employing well matched resistors, impedance of the load to the amplifier can be controlled and common mode feedback loops avoided, because a current source is not employed as a load. The use of parasitic capacitance cancelation capacitors can substantially increase the bandwidth of the amplifier. Furthermore, with transistors, low voltage headroom may be increased and integrated circuit area decreased.

Self-stabilizing differential load circuit with well controlled complex impedance

A circuit includes a bandgap core and a bandgap amplifier. The bandgap core is capable of receiving an input voltage and generating an output voltage. A second-order temperature coefficient in the output voltage is at least partially reduced by the bandgap core while a first-order temperature coefficient in the output voltage remains substantially unchanged.

Circuit and method for reducing reference voltage drift in bandgap circuits

An apparatus and method for producing an output reference voltage is provided. A voltage divider is configured to provide the output reference voltage from a bandgap reference voltage. The bandgap reference voltage is applied across a biased portion of the voltage divider. Additionally, a second-order temperature coefficient (TC) of the impedance of a controllable portion of the voltage divider is adjusted in response to a second-order trim signal. The first and zeroth order TCs of the controllable portion of the voltage divider are substantially independent of the second-order trim signal. In one embodiment, the controllable portion includes a resistor digital-to-analog converter (DAC) that is responsive to the second-order trim signal. The resistor DAC includes at least two different types of resistors. The second-order TCs of the two different types of resistors are substantially different.

Apparatus and method for calibrating a bandgap reference voltage

A half-latch that includes negative feedback circuitry is provided. The negative feedback circuitry causes the steady-state gain of the half-latch to remain high so that the overdrive voltage needed to change the state of the half-latch is significantly reduced. Additionally, the negative feedback is bypassed by capacitors at high frequencies so that the speed of the half-latch is substantially unaffected by the negative feedback.

Apparatus and method for high-speed half-latch with low overdrive voltage

A circuit for providing a self-stabilizing, differential load circuit with well controlled impedance to an amplifier is described. According to one embodiment, two pairs of transistors in a cross-coupled configuration and a degeneration resistor for each transistor provide the self-stabilizing, differential load. Small signal analysis of the circuit illustrates an impedance of the load circuit to be substantially equal to a combination of resistor values with substantially little dependence on transconductances and incremental resistances of the transistors. By employing well matched resistors, impedance of the load to the amplifier may be well controlled, and common mode feedback loops avoided, because a current source is not employed as a load. Furthermore, due to use of transistors, a low voltage headroom may be increased and an integrated circuit area decreased.

Self-stabilizing differential load circuit with well controlled impedance

A biasing circuit is arranged to provide relatively well controlled startup and steady state behavior for a reference circuit such as noise immunity and reduced dependence on supplies. The biasing circuit initially employs an independent bias current for biasing the reference circuit at startup until a large enough bootstrapped (output voltage referenced) bias current can be generated that can take over the subsequent biasing of the circuit in the steady state. In one embodiment, a Power On Reset (POR) signal can be generated during the transition from an initial biasing of the reference circuit by the independent bias current to a subsequent steady state biasing provided by the bootstrapped bias current. Also, the assertion of the POR signal can be employed to turn off the transistors providing the independent bias current.

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Tucson, AZ, United States of America

David James Megaw