International Business Machines Corporation

Other

David James Martens

Michael Kevin Ciraula

Robert Paul Masleid

Terence M Potter

Elan Tsvi Yaniv

An apparatus for mounting an accessory, such as a front stabilizer, to an archery bow allows a wide variety of adjusted positions. The apparatus includes first and second coupling members, a first threaded system for securing the first coupling member to a handle of the archery bow, and a second threaded system for securing the first and second coupling members together. The first threaded system allows the first coupling member to be adjusted about its longitudinal axis relative to the bow handle when loosened, and to be fixed relative to the bow handle when tightened. The second threaded system allows the first and second coupling members to be angularly adjusted relative to each other when loosened, and to be fixed relative to each other when tightened. A front stabilizer or other accessory is secured to the second coupling member.

Apparatus for mounting accessory to archery bow

Each bitslice multiplexing structure of a rotator circuit is configured as a plurality of first stage 8:1 multiplexers each receiving eight of the rotator circuits as inputs and one second-stage 8:1 multiplexer receiving the outputs of the first-stage multiplexers are inputs. To achieve the desired functionality with a single set of shift input signals, the rotator inputs to the first-stage multiplexers are changed for different bitslice multiplexing structures within the rotator, and the connection of the first-stage multiplexer outputs to the second-stage multiplexer inputs are changed for different groups of bitslice multiplexing structures. The first-stage multiplexers are positioned between two input buses running across the entire width of the rotator circuit. Any input of the first-stage multiplexer may be connected a input signal conductor within the input buses above or below the first-stage multiplexer, and the input buses and the first-stage multiplexers are distributed on opposite sides of the second-stage multiplexer. This limits the number of wires required in one metallization level for the vertical direction to twelve at any horizontal cross-section of the bitslice multiplexing structure. The resulting rotator circuit has an improved aspect ratio, more efficient circuit area usage, and better overall circuit performance for performing rotate operations from 0 to 63 bits on 64-bit operands.

Method of wiring a 64-bit rotator to minimize area and maximize performance

An anti-charge share device and method for operation ensure that charge share protection is provided for nodes in a logic circuit during an evaluate stage with low costs in terms of power and circuit performance. The anti-charge sharing device includes a transistor coupled between pre-charge node and a second node being evaluated. By coupling the charge share device between the pre-charge node and the node to be evaluated, operation of the charge share device is dependent upon a node which no longer requires a charge-sharing protection.

Circuit having anti-charge share characteristics and method therefore

A combined adder/decoder calculates a field within an effective address necessary to access a translation array. Rather than adding the full lengths of the previous fetch address and offset, only the bits corresponding to the field are added. A carry-in value from less significant bits is concurrently generated. Based on the sum result, two wordlines are chosen: the wordline corresponding to the sum result calculated and the next higher wordline. The carry-in value is used to select the appropriate wordline from the chosen pair. Because fewer bits are added and the carry-in need not be accounted for in the adder, the generation and decoding processes are faster and allow address translation to be started earlier in the processor cycle.

Translation shadow array adder-decoder circuit for selecting consecutive

An approach for determining whether a current address is within an address range in which both the starting address of the range and the size of the address range are determined by variable register contents. Whereas the information in the variable register contents is in binary format, the current address is in a 2B format. The present invention provides logic for translating the binary formatted information so that it can be compared to the 2B formatted current address.

Block address translation circuit using two-bit to four-bit encoder

An error detection circuit detects single bit errors in arrays containing information encoded in 2B format. The circuit checks for any error where a single bit has been corrupted and detects some types of multiple bit corruptions.

Error detection circuit using two bit to four bit encoder

A dynamic scannable latch circuit for high-speed memory arrays utilized in high-performance integrated circuit devices, wherein the high-speed memory arrays include data-bearing bitlines. The dynamic scannable latch circuit includes a group of scannable latch circuits for serially reading data from high-speed memory arrays during memory-testing cycles wherein each scannable latch circuit provides a scan output to a scan input of a second or next scannable latch circuit in a series of scannable latch circuits. In addition, the dynamic scannable latch circuit includes sensing and combination circuits for sensing the presence of the data-bearing bitlines and for combining the data-bearing bitlines into a memory array output wherein the sensing and combination circuits are coupled to the group of scannable latch circuits. In addition, the sensing and combination circuits further include NAND circuits integrated into a front end of the dynamic scannable latch circuit. Each NAND circuit includes NAND inputs and a NAND output such that each NAND output is coupled to one of the scannable latch circuits among the group of scannable latch circuits. The integration of the NAND circuit into the front end of the dynamic scannable latch circuit reduces the number of transistors utilized to implement the necessary functions for the memory array output and contributes to minimum delay and proper testability.

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Austin, TX, United States of America

David James Martens