Altera Corporation

David James Lau

Jeffrey Orion Pritchard

Philippe Molson

James Loran Ball

Jesse Kempa

Jarrod Colin James Blackburn

Timothy Allen

Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

High-level language code sequence optimization for implementing programmable chip designs

Various high-level languages are used to specify hardware designs on programmable chips. The high-level language programs include pointer operations that may have same iteration and future iteration dependencies. Single loop iteration pointer dependencies are considered when memory accesses are assigned to clock cycles. Multiple loop iteration pointer dependencies are considered when determining how often new data can be entered into the generated hardware pipeline without causing memory corruption. A buffer can be used to forward data from a memory write to a future read.

Scheduling optimization of aliased pointers for implementation on programmable chips

Pipelined loop operations are efficiently scheduled. A preliminary as soon as possible (ASAP) schedule for a data operation in a pipelined loop is determined. A producer operation clock cycle associated with a producer operation in the pipelined loop is determined. The producer operation provides a data value for use by the data operation in a subsequent loop. A consumer operation clock cycle associated with a consumer operation in the pipelined loop is determined. The consumer operation obtains the data value from the data operation in a previous loop. The data operation is scheduled at the half-way point between the producer operation clock cycle and the consumer operation clock cycle.

Scheduling of pipelined loop operations

Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A designer efficiently selects one or more code sequences for acceleration. A hardware accelerator is generated with multiple master ports to allow efficient access to memory. Profiling information can be provided to allow efficient selection of code sequences.

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Scotts Valley, CA, United States of America

David James Lau