International Business Machines Corporation

Globalfoundries Inc.

Other

Globalfoundries U.S. 2 LLC

David James Hathaway

Chandramouli Visweswariah

Kerim Kalafala

Eric A Foreman

Peter Anton Habitz

Jeffrey G Hemmett

Vladimir P Zolotov

John Maxwell Cohn

Anthony D Polson

Natesan Venkateswaran

Alexander Joel Suess

Jerry D Hayes

Alvar Antonio Dean

John P Dubuque

Brian M Dreibelbis

Sebastian Theodore Ventrone

Nathan C Buck

Nathaniel Douglas Hieter

Ronald Dennis Rose

Jeffrey Paul Soreff

Hemlata Gupta

Amir H Farrahi

Shyam Ramji

Patrick M Williams

Scott Alan Tetreault

Thomas M Lepsic

Jun Zhou

Stephen Gerard Shuma

Vasant B Rao

Douglas Willard Stout

David E Lackey

Robert J Allen

Gregory M Schaeffer

Ivan L Wemple

Jagannathan Narasimhan

Nagashyamala R Dhanwada

Jeffrey H Oppold

Mark Alan Lavin

Anthony Richard Bonaccio

Jason D Hibbeler

James A Culp

Arun Joseph

Susan K Lichtensteiger

David Shing-Ki Kung

Douglas Wayne Kemerer

Anthony DeGroff Drumm

Louise Helen Trevillyan

Ricardo H Nigaglioni

Patrick Edward Perry

Roger Paul Gregor

Bhavna Agrawal

Thomas B Chadwick, Jr

William John Livingstone

Wilm Ernst Donath

Margaret R Charlebois

Jason Edward Rotella

Laura S Chadwick

David Wells Winston

Peter James Osler

Pooja M Kotecha

Gaurav Mittal

Cindy ShuiKing Washburn

Charles Jay Alpert

Clarence Rosser Ogilvie

Jeanne P Bickford

Ruchir Puri

Gi-Joon Nam

James Douglas Warnock

Wayne Harvey Woods, Jr

Jinjun Xiong

Paul Gerard Villarrubia

Ulrich Alfons Finkler

Fook-Luen Heng

Steven Frederick Oakland

David S Wolpert

Haoxing Ren

Juergen Koehl

Victor V Zyuban

Prabhakar Nandavar Kudva

Debjit Sinha

Tad Jeffrey Wilder

Sharad Mehrotra

Mark William Kuemerle

Markus Buehler

Vikram Iyengar

Byron Lee Krauter

Sridhar H Rangarajan

Gary Douglas Grise

Larry Wissel

Brion L Keller

Gregory Allen Northrop

Soroush Abbaspour

Jeanne P S Bickford

Chandramouli V Kashyap

Harry John Beatty, Iii

James Charles Gregerson

Philip Neil Strenski

Diyanesh Babu C Vidyapoornachary

Leon Stok

Tsz-mei Ko

Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.

Methods for generating a contributor-based power abstract for a device

A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

Optimizing placement of circuit resources using a globally accessible placement memory

According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Efficient parallel processing of a network with conflict constraints between nodes

A computer program product for performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

System and method for efficient statistical timing analysis of cycle time independent tests

A system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.

Applying random nets credit in an efficient static timing analysis

A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.

Parallel multi-threaded common path pessimism removal in multiple paths

Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit ('IC'); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.

Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit

Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction

Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

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Underhill, VT, United States of America

David James Hathaway