National Semiconductor Corporation

Advanced Micro Devices Corporation

David James Fensore

Robert L Macomber

Gregory Lewis Dean

Kent Bruce Waterson

Alexander Alexeyev

Lawrence D Getzin

David Chaim Brief

James E Schuessler

A device driver which includes an input driver configured to produce a sequence of uncompensated drive signals along with compensation circuitry connected to receive the uncompensated drive signals and to produce corresponding compensated drive signals. The compensation circuitry is capable of storing two or less control points that define a single compensation curve such as a Bezier curve, with the compensation circuitry converting the uncompensated drive signals to the corresponding compensated drive signals utilizing the control points. An output driver is configured to drive a device such as one or more light emitting diodes to be connected to the output driver with the compensated drive signals.

LED driver having non-linear compensation

Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in each segment. The synchronization management bits are programmed such that the synchronization management bits contained in first and second adjacent segments of the serial data stream will bear a predetermined relationship to one another. At the receiving end, the synchronization management bits are examined from segment to segment. In this manner, synchronization can be monitored, synchronization loss can be detected, and synchronization recovery can be achieved.

Low overhead, data transparent synchronization of streaming serial data

Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.

Stacked differential signal transmission circuitry

A method for dynamically selecting a clock edge for recovering read data received from a slave at a master is provided that includes determining whether an internal clock signal is high when a first bit of read data is received at the master. One of a falling edge and a rising edge of the internal clock signal are selected for recovering the read data based on the determination of whether the internal clock signal is high when the first bit of read data is received at the master.

Method and system for dynamically selecting a clock edge for read data recovery

A system includes a memory operable to store scrambled data at a plurality of memory locations. The system also includes an empty detector operable to determine whether a specified memory location is empty using contents of the specified memory location. The contents of the specified memory location are not descrambled for use by the empty detector in determining whether the specified memory location is empty.

System and method for identifying empty locations in a scrambled memory

An apparatus and method for automatically transitioning the operation of an electronic device to a reduced power consumption state if an input reference clock signal is stopped or no longer synchronized (locked) with the operation of the electronic device. The electronic device is automatically returned to a normal operating/power consumption state if the reference clock is restarted. Mixed analog and digital electronic components are employed to handle the transition of the electronic device between reduced and normal power consumption states. These components can include a phase frequency detector and a lost_lock detection circuit. The lost_lock detection circuit is typically connected to the output of phase frequency detector and outputs a lost_lock signal if the reference clock signal has stopped or lost_lock with a feedback clock signal. The lost_lock detection circuit operates on at least one error signal outputted by the phase frequency detector and is relatively insensitive to variations in the duty cycle of the reference and feedback clock signals.

Automatic clock based power-down circuit

A method includes storing data in one of a plurality of memory slots in a queue. Each memory slot is associated with a plurality of flags. The method also includes toggling a first of the flags associated with the slot. The method further includes retrieving the data from the memory slot. In addition, the method includes toggling a second of the flags associated with the slot.

System and method for facilitating communication across an asynchronous clock boundary

A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.

Apparatus and method for initializing a universal serial bus device

A method and apparatus for performing a control transfer on a Universal Serial Bus (USB) device. A USB device includes a memory space for reading and writing data transmitted over a USB network. The memory space is shared between a plurality of endpoints. A host initiates a control transfer by transmitting a SETUP token to a first endpoint. The endpoint must accept the SETUP token. If the first endpoint does not expect the SETUP token, or if another endpoint is active, the device stores the token until a buffer is allocated and the first endpoint is made active.

Growing community of inventors

New Gloucester, ME, United States of America

David James Fensore