Iii Holdings 2, LLC

Advanced Micro Devices Corporation

Legerity, Inc.

Amazon Technologies, Inc.

Other

Siemens Aktiengesellschaft

Morgan Stanley & Co. Incorporated

Calxeda, Inc.

David James Borland

Mark Bradley Davis

Thomas A Volpe

Ken Goss

Arnold Thomas Schnell

Jason Hobbs

Danny Marquette

Ken D Alton

Barry Ross Evans

Joe W Peterson

Gary Michael Godfrey

Paul R Teich

Kenneth S Goss

Richard Owen Waldorf

Tom Volpe

Ron Diamant

Anthony Nicholas Liguori

Randy Renfu Huang

Asif Khan

Nachiketh Rao Potlapally

Richard John Heaton

William John Earl

Derek Del Miller

Rahul Gautam Patel

Uwe Dannowski

Al Hartmann

Edward Davis Geist

Walter Denton Scott

David J Guercio

Jeffrey Carl Defilippi

Paul E Greenwell

Stephan Leonidas Beatty

Bob Dildy

A system on a chip (SoC) can be configured to operate in one of a plurality of modes. In a first mode, the SoC can be operated as a network compute subsystem to provide networking services only. In a second mode, the SoC can be operated as a server compute subsystem to provide compute services only. In a third mode, the SoC can be operated as a network compute subsystem and the server compute subsystem to provide both networking and compute services concurrently.

Multi-mode system on a chip

Systems and methods for performing neural network processing are provided. In one example, a system comprises a neural network processor comprising: a data decryption engine that receives encrypted data and decrypts the encrypted data, the encrypted data comprising at least one of: encrypted weights data, encrypted input data, or encrypted instruction data related to a neural network model; and a computing engine that receives the weights data and perform computations of neural network processing using the input data and the weights data and based on the instruction data.

Secure data processing

Embodiments can provide additional computing resources at minimal and incremental cost by providing instances of one or more server compute subsystems on a system-on-chip. The system-on-chip can include multiple compute subsystems where each compute subsystem can include dedicated processing and memory resources. The system-on-chip can also include a management compute subsystem that can manage the processing and memory resources for each subsystem.

System on a chip comprising multiple compute sub-systems

Embodiments of the technology can provide the flexibility of fine-grained dynamic partitioning of various compute resources among different compute subsystems on an SoC. A plurality of processing cores, cache hierarchies, memory controllers and I/O resources can be dynamically partitioned between a network compute subsystem and a server compute subsystem on the SoC.

System on a chip comprising reconfigurable resources for multiple compute sub-systems

A multi-tenant trusted platform module (MTTPM) is attached to a communication bus of a virtualization host. The MTTPM includes a plurality of per-guest-virtual-machine (per-GVM) memory location sets. In response to an indication of a first trusted computing request (TCR) associated with a first GVM of a plurality of GVMs instantiated at the virtualization host, a first memory location of a first per-GVM memory location set is accessed to generate a first response indicative of a configuration of the first GVM. In response to an indication of a second TCR associated with a second GVM, a second memory location of a second-per-GVM memory location set is accessed to generate a second response, wherein the second response is indicative of a different configuration of the second GVM.

Multi-tenant trusted platform modules

A data processing system includes an enclosure, one or more airflow manifold structures within the enclosure, and a plurality of data processor cards mounted within the enclosure. Each one of the one or more airflow manifold structures has an air inlet portion and an air outlet portion. Each one of the data processor cards extends substantially parallel to each other one of the data processor cards. Each one of the data processor cards includes an airflow duct having an air inlet portion thereof covering a portion of the air outlet portion of at least one of the one or more airflow manifold structures and includes a plurality of data processing units within the airflow duct.

Airflow ducting apparatus for data processing systems

A server apparatus comprises a plurality of server on a chip (SoC) nodes interconnected to each other through a node interconnect fabric. Each one of the SoC nodes has respective memory resources integral therewith. Each one of the SoC nodes has information computing resources accessible by one or more data processing systems. Each one of the SoC nodes configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the SoC nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the SoC nodes thereto based on a workload thereof.

Remote memory access functionality in a cluster of data processing nodes

Techniques are described for logging communication traffic associated with one or more devices. For example, a system bus or other interface to a device may be monitored for traffic data elements. The traffic data elements may include, for example, transaction layer packets (TLPs) for communication across a PCI Express interface, or Ethernet packets for communication over a network. The traffic data elements can be processed by a classifier module and accordingly routed to one of a plurality of circular buffers. The circular buffers may maintain state (e.g., a head pointer and a tail pointer) that identify traffic data elements that are pending and those that are completed. Thus, the circular buffers can be inspected (such as after a crash) to determine recent activity.

Systems and methods for I/O device logging

A data center security system and method are provided that leverage server systems on a chip (SOCs) and/or server fabrics. In more detail, server interconnect fabrics may be leveraged and extended to dramatically improve security within a data center.

System and method for data center security enhancements leveraging server SOCs or server fabrics

A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.

System and method for flexible storage and networking provisioning in large scalable processor installations

A system and method are provided for network proxying. The network proxying may occur in a node of a fabric or across nodes in the fabric. In the network proxying, the node has a processor with a low power mode and the system remaps, by a management processor of the node, a port identifier for a processor that is in a low power mode to the management processor. The management processor then processes a plurality of packets that contain the port identifier for the processor that is in the low power mode to maintain a network presence of the node.

Network proxy for high-performance, low-power data center interconnect fabric

A system for a system and method for provisioning of modular compute resources within a system design are provided.

Node card management in a modular and large scalable server system

System and method for data center security enhancements leveraging managed server SOCs

A performance and power optimized computer system architecture and method leveraging power optimized tree fabric interconnect are disclosed. One embodiment builds low power server clusters leveraging the fabric with tiled building blocks while another embodiment implements storage solutions or cooling solutions. Yet another embodiment uses the fabric to switch non-Ethernet packets, switch multiple protocols for network processors and other devices.

Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

System and method for high-performance, low-power data center interconnect fabric

Growing community of inventors

Austin, TX, United States of America

David James Borland