International Business Machines Corporation

Endicott Interconnect Technologies, Inc.

David James Alcoe

Sanjeev Balwant Sathe

Randall Joseph Stutzman

William Louis Brodsky

Eric A Johnson

David V Caletka

Michael A Gaynes

Kim Joseph Blackwell

Varaprasad Venkata Calmidi

Charles Gerard Woychik

John Steven Kresge

Gerald Walter Jones

Virendra R Jadhav

Francis Joseph Downes, Jr

Varaprasad V Calmidi

Yifan Guo

Cheryl L Tytran-Palomaki

Matthew M Reiss

Steven Wayne Anderson

Thomas W Dalrymple

Stefano Sergio Oggioni

Jeffrey Allen Zitz

Benson Chan

Mario John Interrante

Li Li

William Edward Sablinski

Harvey Charles Hamel

Brenda Lee Peterson

Renee L Weisman

Jeffrey Thomas Coffin

William Infantolino

Francesco Preda

Krishna Darbha

Frank E Andros

Ronald P Nowak

Megan J Shannon

Christopher Todd Spring

A pinned interposer and mating sockets to facilitate removable mounting of high connection density micro devices between a pair of substrates in compact electronic circuit packages. The pinned interposer has an inner set of contacts, typically in a rectangular array, that, in cooperation with a mating socket, allows pluggable connection of a micro device such as a MEMS device connected to a first printed circuit substrate. An outer set of contacts on the interposer provides electrical interconnection between the first substrate and a second substrate located atop the high connection density micro device, thereby effectively sandwiching the micro device between the first and second substrates. The outer set of contacts may be disposed in a circular array.

High density connector for interconnecting fine pitch circuit packaging structures

A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided.

Flexible circuit electronic package with standoffs

An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.

Adjustable thickness thermal interposer and electronic package utilizing same

A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N&#x2267;2) and N metal planes formed in the following sequence: dielectric layeron a metallic plane that exists on a surface of the substrate, metal planeon dielectric layer, dielectric layeron dielectric layerand metal plane, metal planeon the dielectric layer, . . . , dielectric layer N on dielectric layer N&#x2212;1 and metal plane N&#x2212;1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.

Hyperbga buildup laminate

An electronic package having one or more components comprising: a substrate having a first coefficient of thermal expansion; a lid attached to the substrate, the lid including a vapor chamber, the lid having a second coefficient of thermal expansion, the first coefficient of thermal expansion matched to the second coefficient of expansion; a thermal transfer medium in contact with a back surface of each component and an outer surface of a lower wall of the lid; and each component electrically connected to a top surface of the substrate.

Thermally enhanced lid for multichip modules

A test apparatus and method in which a compressible housing is used to retain an electronic component having conductors thereon. The compressible housing is lowered onto a suitable base member having upstanding probes which are also compressible and which physically engage respective ones of the conductors at one end thereof and an appropriate conductor (e.g., conductive pads on a printed circuit board) on the other when the test apparatus is fully assembled and testing occurs.

Electronic component test apparatus

An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.

Electronic package with optimized circuitization pattern

An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad to provide reinforced adhesion of the pad to the substrate to substantially prevent cracking, separation, etc. of the pad when the pad has a pin bonded thereto and the package is coupled to an external substrate (e.g., printed circuit board). The reinforced adhesion also prevents pad separation, etc. during periods of package handling, manufacture, etc.

Pinned electronic package with strengthened conductive pad

An electronic device carrier () adapted for transmitting high-frequency signals, including a circuitized substrate with a plurality of conductive layers (to) insulated from each other, the conductive layers being arranged in a sequence from a first one of the conductive layers () wherein a plurality of signal tracks () each one ending with a contact area () for transmitting a high-frequency signal are formed, and a reference structure () connectable to a reference voltage or ground for shielding the signal tracks the reference structure includes at least one reference track () formed in a second one of the conductive layers () adjacent to the first conductive layer and at least one further reference track formed in one of the conductive layers () different from the first and second conductive layer, a portion of each signal track excluding at least the area corresponding to the orthographic projection of associated contact area being superimposed in plan view to a corresponding reference track and at least a part of the area corresponding to the orthographic projection of the contact area associated to each signal track being superimposed in plan view to a corresponding further reference track with interposition of a floating conductive track, i.e. a track not connected to any signal, reference voltage or ground track.

Electronic device carrier adapted for transmitting high frequency signals

An electronic package includes a substrate having a contact pad thereon, a reformable member such as a solder ball positioned on the contact pad, and an elastic member positioned around the reformable member. The elastic member exerts a girdling force on the reformable member so that when the reformable member is softened, the elastic member elongates the reformable member. This elongation accommodates thermal and other stresses between the foregoing substrate and another substrate joined at the free end of the reformable member. An apparatus is also provided for positioning the elastic member on and around the reformable member.

Method of reforming reformable members of an electronic package and the resultant electronic package

An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.

Electronic package having a thermal stretching layer

A method and structure to adhesively couple a cover plate to a semiconductor device. A semiconductor device is electrically coupled to a substrate. A stiffener ring surrounding the semiconductor device is adhesively coupled to the substrate. A cover plate is adhesively coupled to both a top surface of the semiconductor device and a top surface of the stiffener ring using a first and second adhesive, respectively. The modulus of the first adhesive is less than the modulus of the second adhesive.

Module with adhesively attached heat sink

A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Integrated circuit structure

A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N &#x2267;2) and N metal planes formed in the following sequence: dielectric layeron a metallic plane that exists on a surface of the substrate, metal planeon dielectric layer, dielectric layeron dielectric layerand metal plane, metal planeon the dielectric layer, . . . , dielectric layer N on dielectric layer N-and metal plane N-, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.

Growing community of inventors

Vestal, NY, United States of America

David James Alcoe