Atheros Communications, Inc.

Qualcomm Atheros Inc.

The Connectivity Patent Trust

Qualcomm Incorporated

David J Weber

David Kuochieh Su

Paul J Husted

Manolis Terrovitis

William W Si

Chik Patrick Yue

Patrick Yue

Masound Zargari

William John McFarland

Shahram Abdollahi-Alibeik

Xiaoru Zhang

Soner Ozgur

Masoud Zargari

Lalitkumar Nathawad

MeeLan Lee

Richard T Chang

Meelan Lee

Redundancies of power amplifiers (PAs) or low noise amplifiers (LNAs) at the front end of an RF device are used to reduce losses that typically occur at a diversity switch. A signal designator can advantageously be used to select designated signals, which are provided to the PAs for transmitting or provided by the LNAs during receiving.

Apparatus for signal power loss reduction in RF communication systems

A modulation system comprising a signal processing unit and a modulator. The signal processing unit may generate a low frequency modulator signal, a high frequency modulator signal, and a modulator amplitude control signal. The modulator may generate a modulated signal for transmission via a wireless network based, at least in part, on the low frequency modulator signal, the high frequency modulator signal, and the modulator amplitude control signal. The signal processing unit comprises a delay compensation unit for delaying the generation of the high frequency modulator signal and the modulator amplitude control signal based, at least in part, on signal generation and modulation path delays associated with the low frequency modulator signal to substantially align the modulator signals at the output of the modulation system.

Polar modulator with path delay compensation

A dual mode power amplifier can include a linear gain section and a non-linear gain section configured together as a polar amplifier. The dual mode power amplifier may be used to transmit GFSK, 4-DPSK, and 8-DPSK modulated data. In one mode, both non-linear and linear gain sections may be used to transmit 4-DPSK and 8-DPSK modulated data. Alternatively, in another mode, the linear gain section may be bypassed while the non-linear gain section may be used to transmit GFSK modulated data. By selecting the operating mode, the dual mode power amplifier may be advantageously configured to use relatively less power while supporting GFSK, 4-DPSK, and 8-DPSK modulation schemes.

Dual mode power amplifier

Multiple power amplifiers in an RF front end are coupled to multiple antennas without diversity switching between the PAs and antennas. Diversity switches direct signals to broadcast by a selected antenna to a PA coupled to the selected antenna. Multiple LNAs are similarly coupled to the diverse antennas. Having one PA and LNA set for each antenna removes the need for diversity switching between the PA/LNAs and each antenna improving signal reception. In one embodiment, a single external PA performs broadcast functions and plural on-chip LNAs are used for reception. In another embodiment, phase shifters are coupled to each PA and LNA, which provide beam forming capability for broadcasts, and in phase signal combinations for received signals.

Method and apparatus for signal power loss reduction in RF communication systems

A polar transmitter includes a phase monitoring unit for monitoring input modulating data. When a phase transition exceeds a phase transition threshold, the phase monitor unit can signal an amplitude negation unit to invert the amplitude data coupled to the polar amplifier. The phase monitoring unit can also add an offset to the phase data that is provided to a frequency synthesizer. In another embodiment, when the phase transition threshold is exceeded, the phase monitoring unit can trigger inverting differential frequency data coupled to the polar amplifier. In one embodiment, the phase offset and the amplitude negation are applied until a second phase transition value exceeding the phase transition threshold is detected. If such an event is detected, then the input amplitude data is no longer inverted and the phase offset value is no longer added to the modulating data.

Negative amplitude polar transmitter

An apparatus for processing a Bluetooth signal advantageously mixes down a received RF signal to an IF signal wherein one band-edge of the spectrum of the IF signal may be approximately 0 Hz. In one embodiment, the IF signal may be digitized, decimated and filtered before being processed into a baseband signal. The baseband signal may be processed by a cordic (COordinate Rotation DIgital Computer) processor to transform the baseband signal from rectangular to polar coordinates. A phase signal from the cordic processor may be used to determine transmitted Bluetooth data symbols. The apparatus may advantageously use less area than traditional Bluetooth receivers.

Hybrid zero-IF receiver

A switchable inductor-capacitor-inductor (L-C-L) network, which includes an integrated T/R switch, can advantageously bridge a PA and an LNA of a wireless device. The first inductor can function as an RF choke that provides power to the PA. In one embodiment, the first inductor can be advantageously implemented using the bond wires already attached to the PA, thereby requiring no additional inductors to provide the integrated T/R switch and minimizing use of valuable silicon area. The second inductor can function as a source inductor for and cancel an input parasitic capacitance of the LNA. A set of capacitors can act as blocking capacitors to provide DC isolation between the LNA and the PA, thereby protecting the LNA from high voltages. The L-C-L network can also advantageously function as an impedance matching network for at least one of the PA and the LNA.

Integrated transmitter/receiver switch with impedance matching network

An interleaved ADC can advantageously provide synchronous sampling and time-multiplexed output. Differential I and Q input signals can first be stored by charging a plurality of capacitors. These stored differential signals can be buffered in a time-multiplexed sequence. For example, buffering can include transferring voltages stored by a first set of capacitors at a first time and then transferring voltages stored by a second set of capacitors at a second time. Advantageously, this time-multiplexing allow the ADC to be significantly smaller than conventional implementations of two-input ADCs. A folded mixer with gain control is also provided. This mixer can include a first stage having a first set of inductors and a plurality of first type transistors and a second stage having a second set of inductors and a plurality of second type transistors. The plurality of second type transistors in the second stage, which are in a folded configuration, can be driven by the first set of inductors in the first stage. The outputs of the mixer are positioned between the plurality of second type transistors and the second set of inductors. This configuration advantageously permits the mixer to use a low operating voltage.

Interleaved ADC and folded mixer for WLAN devices

The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

CMOS transceiver having an integrated power amplifier

The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

Growing community of inventors

Santa Clara, CA, United States of America

David J Weber